[llvm-commits] [llvm] r172685 - in /llvm/trunk: lib/Target/Mips/AsmParser/MipsAsmParser.cpp lib/Target/Mips/Disassembler/MipsDisassembler.cpp lib/Target/Mips/MipsRegisterInfo.td test/MC/Disassembler/Mips/mips32.txt test/MC/Disassembler/Mips/mips32_le.txt test/MC/Mips/mips-alu-instructions.s test/MC/Mips/mips64-alu-instructions.s

David Blaikie dblaikie at gmail.com
Tue Aug 6 17:41:59 PDT 2013


Ah, indeed - my mistake. Didn't look at the dates/results properly.

On Tue, Aug 6, 2013 at 5:38 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> This function became unused after r187828.
>
> Thank you for fixing this.
>
>
> On Tue, Aug 6, 2013 at 5:27 PM, David Blaikie <dblaikie at gmail.com> wrote:
>>
>> On Wed, Jan 16, 2013 at 4:28 PM, Jack Carter <jcarter at mips.com> wrote:
>> > Author: jacksprat
>> > Date: Wed Jan 16 18:28:20 2013
>> > New Revision: 172685
>> >
>> > URL: http://llvm.org/viewvc/llvm-project?rev=172685&view=rev
>> > Log:
>> > This is a resubmittal. For some reason it broke the bots yesterday
>> > but I cannot reproduce the problem and have scrubed my sources and
>> > even tested with llvm-lit -v --vg.
>> >
>> > The Mips RDHWR (Read Hardware Register) instruction was not
>> > tested for assembler or dissassembler consumption. This patch
>> > adds that functionality.
>> >
>> > Contributer: Vladimir Medic
>> >
>> >
>> > Modified:
>> >     llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
>> >     llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
>> >     llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
>> >     llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
>> >     llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
>> >     llvm/trunk/test/MC/Mips/mips-alu-instructions.s
>> >     llvm/trunk/test/MC/Mips/mips64-alu-instructions.s
>> >
>> > Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
>> > URL:
>> > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=172685&r1=172684&r2=172685&view=diff
>> >
>> > ==============================================================================
>> > --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
>> > +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Jan 16
>> > 18:28:20 2013
>> > @@ -1045,6 +1045,9 @@
>> >  MipsAsmParser::OperandMatchResultTy
>> >  MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*>
>> > &Operands) {
>> >
>> > +  if (isMips64())
>> > +    return MatchOperand_NoMatch;
>> > +
>> >    // if the first token is not '$' we have error
>> >    if (Parser.getTok().isNot(AsmToken::Dollar))
>> >      return MatchOperand_NoMatch;
>> > @@ -1071,6 +1074,9 @@
>> >
>> >  MipsAsmParser::OperandMatchResultTy
>> >  MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*>
>> > &Operands) {
>> > +
>> > +  if (!isMips64())
>> > +    return MatchOperand_NoMatch;
>> >      //if the first token is not '$' we have error
>> >    if (Parser.getTok().isNot(AsmToken::Dollar))
>> >      return MatchOperand_NoMatch;
>> > @@ -1088,7 +1094,7 @@
>> >
>> >    MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
>> >          Parser.getTok().getLoc());
>> > -  op->setRegKind(MipsOperand::Kind_HWRegs);
>> > +  op->setRegKind(MipsOperand::Kind_HW64Regs);
>> >    Operands.push_back(op);
>> >
>> >    Parser.Lex(); // Eat reg number
>> >
>> > Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
>> > URL:
>> > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=172685&r1=172684&r2=172685&view=diff
>> >
>> > ==============================================================================
>> > --- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
>> > (original)
>> > +++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Wed Jan
>> > 16 18:28:20 2013
>> > @@ -128,6 +128,11 @@
>> >                                                uint64_t Address,
>> >                                                const void *Decoder);
>> >
>> > +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
>> > +                                                unsigned Insn,
>> > +                                                uint64_t Address,
>> > +                                                const void *Decoder);
>> > +
>>
>> This function was/is unused, I removed it in r187838 to clean up the
>> Clang -Werror build.
>>
>> >  static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
>> >                                                unsigned RegNo,
>> >                                                uint64_t Address,
>> > @@ -454,6 +459,17 @@
>> >    return MCDisassembler::Success;
>> >  }
>> >
>> > +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
>> > +                                                unsigned RegNo,
>> > +                                                uint64_t Address,
>> > +                                                const void *Decoder) {
>> > +  //Currently only hardware register 29 is supported
>> > +  if (RegNo != 29)
>> > +    return  MCDisassembler::Fail;
>> > +  Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
>> > +  return MCDisassembler::Success;
>> > +}
>> > +
>> >  static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
>> >                                                unsigned RegNo,
>> >                                                uint64_t Address,
>> >
>> > Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
>> > URL:
>> > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=172685&r1=172684&r2=172685&view=diff
>> >
>> > ==============================================================================
>> > --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
>> > +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Wed Jan 16 18:28:20
>> > 2013
>> > @@ -373,6 +373,6 @@
>> >    let ParserMatchClass = HWRegsAsmOperand;
>> >  }
>> >
>> > -def HW64RegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
>> > +def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
>> >    let ParserMatchClass = HW64RegsAsmOperand;
>> >  }
>> >
>> > Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
>> > URL:
>> > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32.txt?rev=172685&r1=172684&r2=172685&view=diff
>> >
>> > ==============================================================================
>> > --- llvm/trunk/test/MC/Disassembler/Mips/mips32.txt (original)
>> > +++ llvm/trunk/test/MC/Disassembler/Mips/mips32.txt Wed Jan 16 18:28:20
>> > 2013
>> > @@ -404,3 +404,9 @@
>> >
>> >  # CHECK: xori  $9,  $6, 17767
>> >  0x38 0xc9 0x45 0x67
>> > +
>> > +# CHECK: .set    push
>> > +# CHECK: .set    mips32r2
>> > +# CHECK: rdhwr   $5, $29
>> > +# CHECK: .set    pop
>> > +0x7c 0x05 0xe8 0x3b
>> >
>> > Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
>> > URL:
>> > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt?rev=172685&r1=172684&r2=172685&view=diff
>> >
>> > ==============================================================================
>> > --- llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt (original)
>> > +++ llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt Wed Jan 16
>> > 18:28:20 2013
>> > @@ -404,3 +404,9 @@
>> >
>> >  # CHECK: xori  $9,  $6, 17767
>> >  0x67 0x45 0xc9 0x38
>> > +
>> > +# CHECK: .set    push
>> > +# CHECK: .set    mips32r2
>> > +# CHECK: rdhwr   $5, $29
>> > +# CHECK: .set    pop
>> > +0x3b 0xe8 0x05 0x7c
>> >
>> > Modified: llvm/trunk/test/MC/Mips/mips-alu-instructions.s
>> > URL:
>> > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-alu-instructions.s?rev=172685&r1=172684&r2=172685&view=diff
>> >
>> > ==============================================================================
>> > --- llvm/trunk/test/MC/Mips/mips-alu-instructions.s (original)
>> > +++ llvm/trunk/test/MC/Mips/mips-alu-instructions.s Wed Jan 16 18:28:20
>> > 2013
>> > @@ -81,6 +81,10 @@
>> >  # CHECK:  sub     $6, $zero, $7  # encoding: [0x22,0x30,0x07,0x00]
>> >  # CHECK:  subu    $6, $zero, $7  # encoding: [0x23,0x30,0x07,0x00]
>> >  # CHECK:  addu    $7, $8, $zero  # encoding: [0x21,0x38,0x00,0x01]
>> > +# CHECK:  .set    push
>> > +# CHECK:  .set    mips32r2
>> > +# CHECK:  rdhwr   $5, $29
>> > +# CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]
>> >      add    $9,$6,$7
>> >      add    $9,$6,17767
>> >      addu   $9,$6,-15001
>> > @@ -98,3 +102,4 @@
>> >      neg    $6,$7
>> >      negu   $6,$7
>> >      move   $7,$8
>> > +    rdhwr   $5, $29
>> >
>> > Modified: llvm/trunk/test/MC/Mips/mips64-alu-instructions.s
>> > URL:
>> > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64-alu-instructions.s?rev=172685&r1=172684&r2=172685&view=diff
>> >
>> > ==============================================================================
>> > --- llvm/trunk/test/MC/Mips/mips64-alu-instructions.s (original)
>> > +++ llvm/trunk/test/MC/Mips/mips64-alu-instructions.s Wed Jan 16
>> > 18:28:20 2013
>> > @@ -78,6 +78,11 @@
>> >  # CHECK:  multu  $3, $5          # encoding: [0x19,0x00,0x65,0x00]
>> >  # CHECK:  dsubu   $4, $3, $5      # encoding: [0x2f,0x20,0x65,0x00]
>> >  # CHECK:  daddu    $7, $8, $zero  # encoding: [0x2d,0x38,0x00,0x01]
>> > +# CHECK:  .set    push
>> > +# CHECK:  .set    mips32r2
>> > +# CHECK:  rdhwr   $5, $29
>> > +# CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]
>> > +
>> >      dadd    $9,$6,$7
>> >      dadd    $9,$6,17767
>> >      daddu   $9,$6,-15001
>> > @@ -92,3 +97,4 @@
>> >      multu  $3,$5
>> >      dsubu   $4,$3,$5
>> >      move   $7,$8
>> > +    rdhwr   $5, $29
>> >
>> >
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