[llvm] r187800 - [NVPTX] Add missing patterns for i1 [s,u]int_to_fp

[Justin Holewinski]

Author: jholewinski
Date: Tue Aug  6 09:13:34 2013
New Revision: 187800

URL: http://llvm.org/viewvc/llvm-project?rev=187800&view=rev
Log:
[NVPTX] Add missing patterns for i1 [s,u]int_to_fp

Added:
    llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll
Modified:
    llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td

Modified: llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td?rev=187800&r1=187799&r2=187800&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td Tue Aug  6 09:13:34 2013
@@ -2208,6 +2208,17 @@ defm STV_f64 : ST_VEC<Float64Regs>;
 
 //---- Conversion ----
 
+class F_BITCONVERT<string SzStr, NVPTXRegClass regclassIn,
+  NVPTXRegClass regclassOut> :
+           NVPTXInst<(outs regclassOut:$d), (ins regclassIn:$a),
+           !strconcat("mov.b", !strconcat(SzStr, " \t $d, $a;")),
+     [(set regclassOut:$d, (bitconvert regclassIn:$a))]>;
+
+def BITCONVERT_32_I2F : F_BITCONVERT<"32", Int32Regs, Float32Regs>;
+def BITCONVERT_32_F2I : F_BITCONVERT<"32", Float32Regs, Int32Regs>;
+def BITCONVERT_64_I2F : F_BITCONVERT<"64", Int64Regs, Float64Regs>;
+def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;
+
 // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where
 // we cannot specify floating-point literals in isel patterns.  Therefore, we
 // use an integer selp to select either 1 or 0 and then cvt to floating-point.
@@ -2254,6 +2265,8 @@ def : Pat<(f64 (uint_to_fp Int64Regs:$a)
 
 
 // f32 -> sint
+def : Pat<(i1 (fp_to_sint Float32Regs:$a)),
+          (SETP_b32ri (BITCONVERT_32_F2I Float32Regs:$a), 0, CmpEQ)>;
 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
           (CVT_s16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
@@ -2268,6 +2281,8 @@ def : Pat<(i64 (fp_to_sint Float32Regs:$
           (CVT_s64_f32 Float32Regs:$a, CvtRZI)>;
 
 // f32 -> uint
+def : Pat<(i1 (fp_to_uint Float32Regs:$a)),
+          (SETP_b32ri (BITCONVERT_32_F2I Float32Regs:$a), 0, CmpEQ)>;
 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
           (CVT_u16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
@@ -2282,6 +2297,8 @@ def : Pat<(i64 (fp_to_uint Float32Regs:$
           (CVT_u64_f32 Float32Regs:$a, CvtRZI)>;
 
 // f64 -> sint
+def : Pat<(i1 (fp_to_sint Float64Regs:$a)),
+          (SETP_b64ri (BITCONVERT_64_F2I Float64Regs:$a), 0, CmpEQ)>;
 def : Pat<(i16 (fp_to_sint Float64Regs:$a)),
           (CVT_s16_f64 Float64Regs:$a, CvtRZI)>;
 def : Pat<(i32 (fp_to_sint Float64Regs:$a)),
@@ -2290,6 +2307,8 @@ def : Pat<(i64 (fp_to_sint Float64Regs:$
           (CVT_s64_f64 Float64Regs:$a, CvtRZI)>;
 
 // f64 -> uint
+def : Pat<(i1 (fp_to_uint Float64Regs:$a)),
+          (SETP_b64ri (BITCONVERT_64_F2I Float64Regs:$a), 0, CmpEQ)>;
 def : Pat<(i16 (fp_to_uint Float64Regs:$a)),
           (CVT_u16_f64 Float64Regs:$a, CvtRZI)>;
 def : Pat<(i32 (fp_to_uint Float64Regs:$a)),
@@ -2397,17 +2416,6 @@ def : Pat<(select Int32Regs:$pred, Float
           (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
 
 
-class F_BITCONVERT<string SzStr, NVPTXRegClass regclassIn,
-  NVPTXRegClass regclassOut> :
-           NVPTXInst<(outs regclassOut:$d), (ins regclassIn:$a),
-           !strconcat("mov.b", !strconcat(SzStr, " \t $d, $a;")),
-     [(set regclassOut:$d, (bitconvert regclassIn:$a))]>;
-
-def BITCONVERT_32_I2F : F_BITCONVERT<"32", Int32Regs, Float32Regs>;
-def BITCONVERT_32_F2I : F_BITCONVERT<"32", Float32Regs, Int32Regs>;
-def BITCONVERT_64_I2F : F_BITCONVERT<"64", Int64Regs, Float64Regs>;
-def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;
-
 // pack a set of smaller int registers to a larger int register
 def V4I16toI64 : NVPTXInst<(outs Int64Regs:$d),
                           (ins Int16Regs:$s1, Int16Regs:$s2,

Added: llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll?rev=187800&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll (added)
+++ llvm/trunk/test/CodeGen/NVPTX/i1-int-to-fp.ll Tue Aug  6 09:13:34 2013
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+; CHECK-LABEL: foo
+; CHECK: setp
+; CHECK: selp
+; CHECK: cvt.rn.f32.u32
+define float @foo(i1 %a) {
+  %ret = uitofp i1 %a to float
+  ret float %ret
+}
+
+; CHECK-LABEL: foo2
+; CHECK: setp
+; CHECK: selp
+; CHECK: cvt.rn.f32.s32
+define float @foo2(i1 %a) {
+  %ret = sitofp i1 %a to float
+  ret float %ret
+}
+
+; CHECK-LABEL: foo3
+; CHECK: setp
+; CHECK: selp
+; CHECK: cvt.rn.f64.u32
+define double @foo3(i1 %a) {
+  %ret = uitofp i1 %a to double
+  ret double %ret
+}
+
+; CHECK-LABEL: foo4
+; CHECK: setp
+; CHECK: selp
+; CHECK: cvt.rn.f64.s32
+define double @foo4(i1 %a) {
+  %ret = sitofp i1 %a to double
+  ret double %ret
+}