[llvm] r187350 - Some Intel Penryn CPUs come with SSE4 disabled. Detect them as core 2.

[Benjamin Kramer]

On 30.07.2013, at 09:49, Jay Foad <jay.foad at gmail.com> wrote:

> On 29 July 2013 12:02, Benjamin Kramer <benny.kra at googlemail.com> wrote:
>> Author: d0k
>> Date: Mon Jul 29 06:02:08 2013
>> New Revision: 187350
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=187350&view=rev
>> Log:
>> Some Intel Penryn CPUs come with SSE4 disabled.
> 
> ... so wouldn't it be better (or at least less confusing) to change
> this bit of X86.td so that Penryn doesn't imply SSE4?
> 
> def : ProcessorModel<"penryn", SandyBridgeModel,
>                     [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;

The Pentium is an edge case, I think it's better to do the right thing in the common case. Sandy Bridge has the same problem.

- Ben