R600: Scheduling support for VLIW5 gen

[Tom Stellard]

On Mon, Jul 29, 2013 at 12:42:59PM -0700, Tom Stellard wrote:
> On Fri, Jul 26, 2013 at 07:00:27AM -0700, Vincent Lejeune wrote:
> > Hi,
> > 
> > the first 2 patches in this serie make our scheduler properly support vliw5 hardware. Previously a vliw4 was always assumed;
> > it was compatible with vliw5 scheduling but provided not optimal performance as the transALU slot was never used.
> > 
> > The last patch is a more general performance improvement that increase performance in Lightmark 2008, and the other one
> > just make sure that there is never more than 4 litteral in a single ig instead of crashing at R600ControlFlowFinalizer.
> > 
> > Vincent
> 
> > From 13b24a905a9e61b354df4f24400fdc501d77fa51 Mon Sep 17 00:00:00 2001
> > From: Vincent Lejeune <vljn at ovi.com>
> > Date: Wed, 26 Jun 2013 18:32:52 +0200
> > Subject: [PATCH 2/4] R600: Non vector only instruction can be scheduled on
> >  trans unit
> > 
> 
> It would be nice to have a test for this.  You should be able to write a
> simple one with 5 fmul instructions.
> 
> Other than that the series is:
> 
> Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> 
> I still would like to test this on r600g with compute, so I'll let you
> know when I've finished.
> 

There are a few regressions with this branch.  It looks like some ALU
instructions are being emitted after trans-only instructions like MULLO_INT.
See the attached test case.  It would be great if you could reduce this
to something smaller but either way the test should be added to the
revised commit.

-Tom
-------------- next part --------------
; ModuleID = 'radeon'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
target triple = "r600--"

; Function Attrs: nounwind
define void @fill3d(i32 addrspace(1)* nocapture %out) #0 {
entry:
  %x.i = tail call i32 @llvm.r600.read.global.size.x() #1
  %y.i18 = tail call i32 @llvm.r600.read.global.size.y() #1
  %mul = mul i32 %y.i18, %x.i
  %z.i17 = tail call i32 @llvm.r600.read.global.size.z() #1
  %mul3 = mul i32 %mul, %z.i17
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i16 = add i32 %x.i4.i, %mul26.i
  %mul7 = mul i32 %add.i16, %y.i18
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i14 = add i32 %mul30.i, %mul7
  %mul819 = add i32 %add.i14, %y.i6.i
  %add = mul i32 %mul819, %z.i17
  %z.i.i = tail call i32 @llvm.r600.read.tgid.z() #1
  %z.i16.i = tail call i32 @llvm.r600.read.local.size.z() #1
  %mul33.i = mul i32 %z.i16.i, %z.i.i
  %z.i8.i = tail call i32 @llvm.r600.read.tidig.z() #1
  %add.i = add i32 %z.i8.i, %mul33.i
  %add13 = add i32 %add.i, %add
  %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %add13
  store i32 %mul3, i32 addrspace(1)* %arrayidx, align 4, !tbaa !3
  ret void
}

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tgid.x() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tgid.y() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tgid.z() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.local.size.x() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.local.size.y() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.local.size.z() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tidig.x() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tidig.y() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tidig.z() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.global.size.x() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.global.size.y() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.global.size.z() #1

attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }

!opencl.kernels = !{!0, !1, !2}

!0 = metadata !{null}
!1 = metadata !{null}
!2 = metadata !{void (i32 addrspace(1)*)* @fill3d}
!3 = metadata !{metadata !"int", metadata !4}
!4 = metadata !{metadata !"omnipotent char", metadata !5}
!5 = metadata !{metadata !"Simple C/C++ TBAA"}