[llvm] r187112 - [SystemZ] Add LOC and LOCG
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Thu Jul 25 02:04:53 PDT 2013
Author: rsandifo
Date: Thu Jul 25 04:04:52 2013
New Revision: 187112
URL: http://llvm.org/viewvc/llvm-project?rev=187112&view=rev
Log:
[SystemZ] Add LOC and LOCG
As with the stores, these instructions can trap when the condition is false,
so they are only used for things like (cond ? x : *ptr).
Added:
llvm/trunk/test/CodeGen/SystemZ/cond-load-01.ll
llvm/trunk/test/CodeGen/SystemZ/cond-load-02.ll
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZOperands.td
llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
llvm/trunk/test/MC/SystemZ/insn-good-z196.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=187112&r1=187111&r2=187112&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Thu Jul 25 04:04:52 2013
@@ -704,6 +704,46 @@ class UnaryRILPC<string mnemonic, bits<1
let AddedComplexity = 7;
}
+class CondUnaryRSY<string mnemonic, bits<16> opcode,
+ RegisterOperand cls, bits<5> bytes,
+ AddressingMode mode = bdaddr20only>
+ : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, cond4:$R3),
+ mnemonic#"$R3\t$R1, $BD2", []>,
+ Requires<[FeatureLoadStoreOnCond]> {
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+ let mayLoad = 1;
+ let AccessBytes = bytes;
+}
+
+// Like CondUnaryRSY, but used for the raw assembly form. The condition-code
+// mask is the third operand rather than being part of the mnemonic.
+class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
+ RegisterOperand cls, bits<5> bytes,
+ AddressingMode mode = bdaddr20only>
+ : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, uimm8zx4:$R3),
+ mnemonic#"\t$R1, $BD2, $R3", []>,
+ Requires<[FeatureLoadStoreOnCond]> {
+ let mayLoad = 1;
+ let AccessBytes = bytes;
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+}
+
+// Like CondUnaryRSY, but with a fixed CC mask.
+class FixedCondUnaryRSY<string mnemonic, bits<16> opcode,
+ RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
+ AddressingMode mode = bdaddr20only>
+ : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
+ mnemonic#"\t$R1, $BD2", []>,
+ Requires<[FeatureLoadStoreOnCond]> {
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+ let R3 = ccmask;
+ let mayLoad = 1;
+ let AccessBytes = bytes;
+}
+
class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdxaddr12only>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=187112&r1=187111&r2=187112&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Thu Jul 25 04:04:52 2013
@@ -112,6 +112,8 @@ multiclass CondExtendedMnemonic<bits<4>
def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
"jg"##name##"\t$I2", []>;
}
+ def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
+ def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
}
@@ -259,6 +261,18 @@ let canFoldAsLoad = 1 in {
def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
}
+// Load on condition.
+let isCodeGenOnly = 1, Uses = [CC] in {
+ def LOC : CondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
+ def LOCG : CondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
+}
+let Uses = [CC] in {
+ def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
+ def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
+}
+defm : CondLoad<LOC, GR32, nonvolatile_load>;
+defm : CondLoad<LOCG, GR64, nonvolatile_load>;
+
// Register stores.
let SimpleBDXStore = 1 in {
let isCodeGenOnly = 1 in
Modified: llvm/trunk/lib/Target/SystemZ/SystemZOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZOperands.td?rev=187112&r1=187111&r2=187112&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZOperands.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZOperands.td Thu Jul 25 04:04:52 2013
@@ -111,6 +111,15 @@ class BDLMode<string type, string bitsiz
!cast<Immediate>("imm"##bitsize))>;
//===----------------------------------------------------------------------===//
+// Manipulating CC masks
+//===----------------------------------------------------------------------===//
+
+def INVCC : SDNodeXForm<imm, [{
+ unsigned Value = N->getZExtValue() ^ SystemZ::CCMASK_ANY;
+ return CurDAG->getTargetConstant(Value, MVT::i8);
+}]>;
+
+//===----------------------------------------------------------------------===//
// Extracting immediate operands from nodes
// These all create MVT::i64 nodes to ensure the value is not sign-extended
// when converted from an SDNode to a MachineOperand later on.
Modified: llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td?rev=187112&r1=187111&r2=187112&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td Thu Jul 25 04:04:52 2013
@@ -54,6 +54,18 @@ multiclass RMWIByte<SDPatternOperator op
def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
}
+// Record that INSN conditionally performs load operation LOAD into a
+// register of class CLS. The load may trap even if the condition is false.
+multiclass CondLoad<Instruction insn, RegisterOperand cls,
+ SDPatternOperator load> {
+ def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4:$cc),
+ (insn cls:$new, bdaddr20only:$addr, uimm8zx4:$cc)>,
+ Requires<[FeatureLoadStoreOnCond]>;
+ def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4:$cc),
+ (insn cls:$new, bdaddr20only:$addr, (INVCC uimm8zx4:$cc))>,
+ Requires<[FeatureLoadStoreOnCond]>;
+}
+
// Record that INSN performs insertion TYPE into a register of class CLS.
// The inserted operand is loaded using LOAD from an address of mode MODE.
multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
Added: llvm/trunk/test/CodeGen/SystemZ/cond-load-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-load-01.ll?rev=187112&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-load-01.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-load-01.ll Thu Jul 25 04:04:52 2013
@@ -0,0 +1,130 @@
+; Test LOC.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i32 @foo(i32 *)
+
+; Test the simple case.
+define i32 @f1(i32 %easy, i32 *%ptr, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK: clfi %r4, 42
+; CHECK: locnl %r2, 0(%r3)
+; CHECK: br %r14
+ %cond = icmp ult i32 %limit, 42
+ %other = load i32 *%ptr
+ %res = select i1 %cond, i32 %easy, i32 %other
+ ret i32 %res
+}
+
+; ...and again with the operands swapped.
+define i32 @f2(i32 %easy, i32 *%ptr, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK: clfi %r4, 42
+; CHECK: locl %r2, 0(%r3)
+; CHECK: br %r14
+ %cond = icmp ult i32 %limit, 42
+ %other = load i32 *%ptr
+ %res = select i1 %cond, i32 %other, i32 %easy
+ ret i32 %res
+}
+
+; Check the high end of the aligned LOC range.
+define i32 @f3(i32 %easy, i32 *%base, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: clfi %r4, 42
+; CHECK: locnl %r2, 524284(%r3)
+; CHECK: br %r14
+ %ptr = getelementptr i32 *%base, i64 131071
+ %cond = icmp ult i32 %limit, 42
+ %other = load i32 *%ptr
+ %res = select i1 %cond, i32 %easy, i32 %other
+ ret i32 %res
+}
+
+; Check the next word up. Other sequences besides this one would be OK.
+define i32 @f4(i32 %easy, i32 *%base, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: agfi %r3, 524288
+; CHECK: clfi %r4, 42
+; CHECK: locnl %r2, 0(%r3)
+; CHECK: br %r14
+ %ptr = getelementptr i32 *%base, i64 131072
+ %cond = icmp ult i32 %limit, 42
+ %other = load i32 *%ptr
+ %res = select i1 %cond, i32 %easy, i32 %other
+ ret i32 %res
+}
+
+; Check the low end of the LOC range.
+define i32 @f5(i32 %easy, i32 *%base, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK: clfi %r4, 42
+; CHECK: locnl %r2, -524288(%r3)
+; CHECK: br %r14
+ %ptr = getelementptr i32 *%base, i64 -131072
+ %cond = icmp ult i32 %limit, 42
+ %other = load i32 *%ptr
+ %res = select i1 %cond, i32 %easy, i32 %other
+ ret i32 %res
+}
+
+; Check the next word down, with the same comments as f4.
+define i32 @f6(i32 %easy, i32 *%base, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK: agfi %r3, -524292
+; CHECK: clfi %r4, 42
+; CHECK: locnl %r2, 0(%r3)
+; CHECK: br %r14
+ %ptr = getelementptr i32 *%base, i64 -131073
+ %cond = icmp ult i32 %limit, 42
+ %other = load i32 *%ptr
+ %res = select i1 %cond, i32 %easy, i32 %other
+ ret i32 %res
+}
+
+; Try a frame index base.
+define i32 @f7(i32 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo at PLT
+; CHECK: locnl %r2, {{[0-9]+}}(%r15)
+; CHECK: br %r14
+ %ptr = alloca i32
+ %easy = call i32 @foo(i32 *%ptr)
+ %cond = icmp ult i32 %limit, 42
+ %other = load i32 *%ptr
+ %res = select i1 %cond, i32 %easy, i32 %other
+ ret i32 %res
+}
+
+; Try a case when an index is involved.
+define i32 @f8(i32 %easy, i32 %limit, i64 %base, i64 %index) {
+; CHECK-LABEL: f8:
+; CHECK: clfi %r3, 42
+; CHECK: locnl %r2, 0({{%r[1-5]}})
+; CHECK: br %r14
+ %add = add i64 %base, %index
+ %ptr = inttoptr i64 %add to i32 *
+ %cond = icmp ult i32 %limit, 42
+ %other = load i32 *%ptr
+ %res = select i1 %cond, i32 %easy, i32 %other
+ ret i32 %res
+}
+
+; Test that conditionally-executed loads do not use LOC, since it is allowed
+; to trap even when the condition is false.
+define i32 @f9(i32 %easy, i32 %limit, i32 *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: loc
+; CHECK: br %r14
+entry:
+ %cmp = icmp ule i32 %easy, %limit
+ br i1 %cmp, label %load, label %exit
+
+load:
+ %other = load i32 *%ptr
+ br label %exit
+
+exit:
+ %res = phi i32 [ %easy, %entry ], [ %other, %load ]
+ ret i32 %res
+}
Added: llvm/trunk/test/CodeGen/SystemZ/cond-load-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-load-02.ll?rev=187112&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-load-02.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-load-02.ll Thu Jul 25 04:04:52 2013
@@ -0,0 +1,130 @@
+; Test LOCG.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i64 @foo(i64 *)
+
+; Test the simple case.
+define i64 @f1(i64 %easy, i64 *%ptr, i64 %limit) {
+; CHECK-LABEL: f1:
+; CHECK: clgfi %r4, 42
+; CHECK: locgnl %r2, 0(%r3)
+; CHECK: br %r14
+ %cond = icmp ult i64 %limit, 42
+ %other = load i64 *%ptr
+ %res = select i1 %cond, i64 %easy, i64 %other
+ ret i64 %res
+}
+
+; ...and again with the operands swapped.
+define i64 @f2(i64 %easy, i64 *%ptr, i64 %limit) {
+; CHECK-LABEL: f2:
+; CHECK: clgfi %r4, 42
+; CHECK: locgl %r2, 0(%r3)
+; CHECK: br %r14
+ %cond = icmp ult i64 %limit, 42
+ %other = load i64 *%ptr
+ %res = select i1 %cond, i64 %other, i64 %easy
+ ret i64 %res
+}
+
+; Check the high end of the aligned LOCG range.
+define i64 @f3(i64 %easy, i64 *%base, i64 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: clgfi %r4, 42
+; CHECK: locgnl %r2, 524280(%r3)
+; CHECK: br %r14
+ %ptr = getelementptr i64 *%base, i64 65535
+ %cond = icmp ult i64 %limit, 42
+ %other = load i64 *%ptr
+ %res = select i1 %cond, i64 %easy, i64 %other
+ ret i64 %res
+}
+
+; Check the next doubleword up. Other sequences besides this one would be OK.
+define i64 @f4(i64 %easy, i64 *%base, i64 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: agfi %r3, 524288
+; CHECK: clgfi %r4, 42
+; CHECK: locgnl %r2, 0(%r3)
+; CHECK: br %r14
+ %ptr = getelementptr i64 *%base, i64 65536
+ %cond = icmp ult i64 %limit, 42
+ %other = load i64 *%ptr
+ %res = select i1 %cond, i64 %easy, i64 %other
+ ret i64 %res
+}
+
+; Check the low end of the LOCG range.
+define i64 @f5(i64 %easy, i64 *%base, i64 %limit) {
+; CHECK-LABEL: f5:
+; CHECK: clgfi %r4, 42
+; CHECK: locgnl %r2, -524288(%r3)
+; CHECK: br %r14
+ %ptr = getelementptr i64 *%base, i64 -65536
+ %cond = icmp ult i64 %limit, 42
+ %other = load i64 *%ptr
+ %res = select i1 %cond, i64 %easy, i64 %other
+ ret i64 %res
+}
+
+; Check the next doubleword down, with the same comments as f4.
+define i64 @f6(i64 %easy, i64 *%base, i64 %limit) {
+; CHECK-LABEL: f6:
+; CHECK: agfi %r3, -524296
+; CHECK: clgfi %r4, 42
+; CHECK: locgnl %r2, 0(%r3)
+; CHECK: br %r14
+ %ptr = getelementptr i64 *%base, i64 -65537
+ %cond = icmp ult i64 %limit, 42
+ %other = load i64 *%ptr
+ %res = select i1 %cond, i64 %easy, i64 %other
+ ret i64 %res
+}
+
+; Try a frame index base.
+define i64 @f7(i64 %alt, i64 %limit) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo at PLT
+; CHECK: locgnl %r2, {{[0-9]+}}(%r15)
+; CHECK: br %r14
+ %ptr = alloca i64
+ %easy = call i64 @foo(i64 *%ptr)
+ %cond = icmp ult i64 %limit, 42
+ %other = load i64 *%ptr
+ %res = select i1 %cond, i64 %easy, i64 %other
+ ret i64 %res
+}
+
+; Try a case when an index is involved.
+define i64 @f8(i64 %easy, i64 %limit, i64 %base, i64 %index) {
+; CHECK-LABEL: f8:
+; CHECK: clgfi %r3, 42
+; CHECK: locgnl %r2, 0({{%r[1-5]}})
+; CHECK: br %r14
+ %add = add i64 %base, %index
+ %ptr = inttoptr i64 %add to i64 *
+ %cond = icmp ult i64 %limit, 42
+ %other = load i64 *%ptr
+ %res = select i1 %cond, i64 %easy, i64 %other
+ ret i64 %res
+}
+
+; Test that conditionally-executed loads do not use LOCG, since it is allowed
+; to trap even when the condition is false.
+define i64 @f9(i64 %easy, i64 %limit, i64 *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: locg
+; CHECK: br %r14
+entry:
+ %cmp = icmp ule i64 %easy, %limit
+ br i1 %cmp, label %load, label %exit
+
+load:
+ %other = load i64 *%ptr
+ br label %exit
+
+exit:
+ %res = phi i64 [ %easy, %entry ], [ %other, %load ]
+ ret i64 %res
+}
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=187112&r1=187111&r2=187112&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Thu Jul 25 04:04:52 2013
@@ -3262,6 +3262,102 @@
# CHECK: lnxbr %f13, %f9
0xb3 0x41 0x00 0xd9
+# CHECK: loc %r7, 6399(%r8), 0
+0xeb 0x70 0x88 0xff 0x01 0xf2
+
+# CHECK: loco %r7, 6399(%r8)
+0xeb 0x71 0x88 0xff 0x01 0xf2
+
+# CHECK: loch %r7, 6399(%r8)
+0xeb 0x72 0x88 0xff 0x01 0xf2
+
+# CHECK: locnle %r7, 6399(%r8)
+0xeb 0x73 0x88 0xff 0x01 0xf2
+
+# CHECK: locl %r7, 6399(%r8)
+0xeb 0x74 0x88 0xff 0x01 0xf2
+
+# CHECK: locnhe %r7, 6399(%r8)
+0xeb 0x75 0x88 0xff 0x01 0xf2
+
+# CHECK: loclh %r7, 6399(%r8)
+0xeb 0x76 0x88 0xff 0x01 0xf2
+
+# CHECK: locne %r7, 6399(%r8)
+0xeb 0x77 0x88 0xff 0x01 0xf2
+
+# CHECK: loce %r7, 6399(%r8)
+0xeb 0x78 0x88 0xff 0x01 0xf2
+
+# CHECK: locnlh %r7, 6399(%r8)
+0xeb 0x79 0x88 0xff 0x01 0xf2
+
+# CHECK: loche %r7, 6399(%r8)
+0xeb 0x7a 0x88 0xff 0x01 0xf2
+
+# CHECK: locnl %r7, 6399(%r8)
+0xeb 0x7b 0x88 0xff 0x01 0xf2
+
+# CHECK: locle %r7, 6399(%r8)
+0xeb 0x7c 0x88 0xff 0x01 0xf2
+
+# CHECK: locnh %r7, 6399(%r8)
+0xeb 0x7d 0x88 0xff 0x01 0xf2
+
+# CHECK: locno %r7, 6399(%r8)
+0xeb 0x7e 0x88 0xff 0x01 0xf2
+
+# CHECK: loc %r7, 6399(%r8), 15
+0xeb 0x7f 0x88 0xff 0x01 0xf2
+
+# CHECK: locg %r7, 6399(%r8), 0
+0xeb 0x70 0x88 0xff 0x01 0xe2
+
+# CHECK: locgo %r7, 6399(%r8)
+0xeb 0x71 0x88 0xff 0x01 0xe2
+
+# CHECK: locgh %r7, 6399(%r8)
+0xeb 0x72 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnle %r7, 6399(%r8)
+0xeb 0x73 0x88 0xff 0x01 0xe2
+
+# CHECK: locgl %r7, 6399(%r8)
+0xeb 0x74 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnhe %r7, 6399(%r8)
+0xeb 0x75 0x88 0xff 0x01 0xe2
+
+# CHECK: locglh %r7, 6399(%r8)
+0xeb 0x76 0x88 0xff 0x01 0xe2
+
+# CHECK: locgne %r7, 6399(%r8)
+0xeb 0x77 0x88 0xff 0x01 0xe2
+
+# CHECK: locge %r7, 6399(%r8)
+0xeb 0x78 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnlh %r7, 6399(%r8)
+0xeb 0x79 0x88 0xff 0x01 0xe2
+
+# CHECK: locghe %r7, 6399(%r8)
+0xeb 0x7a 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnl %r7, 6399(%r8)
+0xeb 0x7b 0x88 0xff 0x01 0xe2
+
+# CHECK: locgle %r7, 6399(%r8)
+0xeb 0x7c 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnh %r7, 6399(%r8)
+0xeb 0x7d 0x88 0xff 0x01 0xe2
+
+# CHECK: locgno %r7, 6399(%r8)
+0xeb 0x7e 0x88 0xff 0x01 0xe2
+
+# CHECK: locg %r7, 6399(%r8), 15
+0xeb 0x7f 0x88 0xff 0x01 0xe2
+
# CHECK: lpdbr %f0, %f9
0xb3 0x10 0x00 0x09
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-z196.s?rev=187112&r1=187111&r2=187112&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-z196.s Thu Jul 25 04:04:52 2013
@@ -25,6 +25,40 @@
ahik %r0, %r1, foo
#CHECK: error: invalid operand
+#CHECK: loc %r0,0,-1
+#CHECK: error: invalid operand
+#CHECK: loc %r0,0,16
+#CHECK: error: invalid operand
+#CHECK: loc %r0,-524289,1
+#CHECK: error: invalid operand
+#CHECK: loc %r0,524288,1
+#CHECK: error: invalid use of indexed addressing
+#CHECK: loc %r0,0(%r1,%r2),1
+
+ loc %r0,0,-1
+ loc %r0,0,16
+ loc %r0,-524289,1
+ loc %r0,524288,1
+ loc %r0,0(%r1,%r2),1
+
+#CHECK: error: invalid operand
+#CHECK: locg %r0,0,-1
+#CHECK: error: invalid operand
+#CHECK: locg %r0,0,16
+#CHECK: error: invalid operand
+#CHECK: locg %r0,-524289,1
+#CHECK: error: invalid operand
+#CHECK: locg %r0,524288,1
+#CHECK: error: invalid use of indexed addressing
+#CHECK: locg %r0,0(%r1,%r2),1
+
+ locg %r0,0,-1
+ locg %r0,0,16
+ locg %r0,-524289,1
+ locg %r0,524288,1
+ locg %r0,0(%r1,%r2),1
+
+#CHECK: error: invalid operand
#CHECK: sllk %r0,%r0,-524289
#CHECK: error: invalid operand
#CHECK: sllk %r0,%r0,524288
Modified: llvm/trunk/test/MC/SystemZ/insn-good-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z196.s?rev=187112&r1=187111&r2=187112&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z196.s Thu Jul 25 04:04:52 2013
@@ -121,6 +121,102 @@
ark %r15,%r0,%r0
ark %r7,%r8,%r9
+#CHECK: loc %r0, 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xf2]
+#CHECK: loc %r0, 0, 15 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xf2]
+#CHECK: loc %r0, -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xf2]
+#CHECK: loc %r0, 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xf2]
+#CHECK: loc %r0, 0(%r1), 0 # encoding: [0xeb,0x00,0x10,0x00,0x00,0xf2]
+#CHECK: loc %r0, 0(%r15), 0 # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xf2]
+#CHECK: loc %r15, 0, 0 # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xf2]
+#CHECK: loc %r1, 4095(%r2), 3 # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xf2]
+
+ loc %r0,0,0
+ loc %r0,0,15
+ loc %r0,-524288,0
+ loc %r0,524287,0
+ loc %r0,0(%r1),0
+ loc %r0,0(%r15),0
+ loc %r15,0,0
+ loc %r1,4095(%r2),3
+
+#CHECK: loco %r1, 2(%r3) # encoding: [0xeb,0x11,0x30,0x02,0x00,0xf2]
+#CHECK: loch %r1, 2(%r3) # encoding: [0xeb,0x12,0x30,0x02,0x00,0xf2]
+#CHECK: locnle %r1, 2(%r3) # encoding: [0xeb,0x13,0x30,0x02,0x00,0xf2]
+#CHECK: locl %r1, 2(%r3) # encoding: [0xeb,0x14,0x30,0x02,0x00,0xf2]
+#CHECK: locnhe %r1, 2(%r3) # encoding: [0xeb,0x15,0x30,0x02,0x00,0xf2]
+#CHECK: loclh %r1, 2(%r3) # encoding: [0xeb,0x16,0x30,0x02,0x00,0xf2]
+#CHECK: locne %r1, 2(%r3) # encoding: [0xeb,0x17,0x30,0x02,0x00,0xf2]
+#CHECK: loce %r1, 2(%r3) # encoding: [0xeb,0x18,0x30,0x02,0x00,0xf2]
+#CHECK: locnlh %r1, 2(%r3) # encoding: [0xeb,0x19,0x30,0x02,0x00,0xf2]
+#CHECK: loche %r1, 2(%r3) # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xf2]
+#CHECK: locnl %r1, 2(%r3) # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xf2]
+#CHECK: locle %r1, 2(%r3) # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xf2]
+#CHECK: locnh %r1, 2(%r3) # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xf2]
+#CHECK: locno %r1, 2(%r3) # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xf2]
+
+ loco %r1,2(%r3)
+ loch %r1,2(%r3)
+ locnle %r1,2(%r3)
+ locl %r1,2(%r3)
+ locnhe %r1,2(%r3)
+ loclh %r1,2(%r3)
+ locne %r1,2(%r3)
+ loce %r1,2(%r3)
+ locnlh %r1,2(%r3)
+ loche %r1,2(%r3)
+ locnl %r1,2(%r3)
+ locle %r1,2(%r3)
+ locnh %r1,2(%r3)
+ locno %r1,2(%r3)
+
+#CHECK: locg %r0, 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xe2]
+#CHECK: locg %r0, 0, 15 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xe2]
+#CHECK: locg %r0, -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xe2]
+#CHECK: locg %r0, 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xe2]
+#CHECK: locg %r0, 0(%r1), 0 # encoding: [0xeb,0x00,0x10,0x00,0x00,0xe2]
+#CHECK: locg %r0, 0(%r15), 0 # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xe2]
+#CHECK: locg %r15, 0, 0 # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xe2]
+#CHECK: locg %r1, 4095(%r2), 3 # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xe2]
+
+ locg %r0,0,0
+ locg %r0,0,15
+ locg %r0,-524288,0
+ locg %r0,524287,0
+ locg %r0,0(%r1),0
+ locg %r0,0(%r15),0
+ locg %r15,0,0
+ locg %r1,4095(%r2),3
+
+#CHECK: locgo %r1, 2(%r3) # encoding: [0xeb,0x11,0x30,0x02,0x00,0xe2]
+#CHECK: locgh %r1, 2(%r3) # encoding: [0xeb,0x12,0x30,0x02,0x00,0xe2]
+#CHECK: locgnle %r1, 2(%r3) # encoding: [0xeb,0x13,0x30,0x02,0x00,0xe2]
+#CHECK: locgl %r1, 2(%r3) # encoding: [0xeb,0x14,0x30,0x02,0x00,0xe2]
+#CHECK: locgnhe %r1, 2(%r3) # encoding: [0xeb,0x15,0x30,0x02,0x00,0xe2]
+#CHECK: locglh %r1, 2(%r3) # encoding: [0xeb,0x16,0x30,0x02,0x00,0xe2]
+#CHECK: locgne %r1, 2(%r3) # encoding: [0xeb,0x17,0x30,0x02,0x00,0xe2]
+#CHECK: locge %r1, 2(%r3) # encoding: [0xeb,0x18,0x30,0x02,0x00,0xe2]
+#CHECK: locgnlh %r1, 2(%r3) # encoding: [0xeb,0x19,0x30,0x02,0x00,0xe2]
+#CHECK: locghe %r1, 2(%r3) # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xe2]
+#CHECK: locgnl %r1, 2(%r3) # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xe2]
+#CHECK: locgle %r1, 2(%r3) # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xe2]
+#CHECK: locgnh %r1, 2(%r3) # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xe2]
+#CHECK: locgno %r1, 2(%r3) # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xe2]
+
+ locgo %r1,2(%r3)
+ locgh %r1,2(%r3)
+ locgnle %r1,2(%r3)
+ locgl %r1,2(%r3)
+ locgnhe %r1,2(%r3)
+ locglh %r1,2(%r3)
+ locgne %r1,2(%r3)
+ locge %r1,2(%r3)
+ locgnlh %r1,2(%r3)
+ locghe %r1,2(%r3)
+ locgnl %r1,2(%r3)
+ locgle %r1,2(%r3)
+ locgnh %r1,2(%r3)
+ locgno %r1,2(%r3)
+
#CHECK: ngrk %r0, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0x00]
#CHECK: ngrk %r0, %r0, %r15 # encoding: [0xb9,0xe4,0xf0,0x00]
#CHECK: ngrk %r0, %r15, %r0 # encoding: [0xb9,0xe4,0x00,0x0f]
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