[llvm] r186661 - Improve llvm-mc disassembler mode and refactor ARM tests to use it
Tim Northover
tnorthover at apple.com
Fri Jul 19 03:05:04 PDT 2013
Author: tnorthover
Date: Fri Jul 19 05:05:04 2013
New Revision: 186661
URL: http://llvm.org/viewvc/llvm-project?rev=186661&view=rev
Log:
Improve llvm-mc disassembler mode and refactor ARM tests to use it
This allows "llvm-mc -disassemble" to accept two new features:
+ Using comma as a byte separator
+ Grouping bytes with '[' and ']' pairs.
The behaviour outside a [...] group is unchanged. But within the group once
llvm-mc encounters a true error, it stops rather than trying to resynchronise
the stream at the next byte. This is more useful for disassembly tests, where
we have an almost-instruction in mind and don't care what the misaligned
interpretation would be. Particularly if it means llvm-mc won't actually see
the next intended almost-instruction.
As a side effect, this means llvm-mc can disassemble its own -show-encoding
output if copy-pasted.
Added:
llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt
Removed:
llvm/trunk/test/MC/Disassembler/ARM/invalid-BFI-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-CDP2-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-MCR-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-STR-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-v8fp.txt
Modified:
llvm/trunk/tools/llvm-mc/Disassembler.cpp
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-BFI-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-BFI-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-BFI-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-BFI-arm.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if d == 15 then UNPREDICTABLE;
-0x16 0xf0 0xcf 0xe7
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-CDP2-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CDP2-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CDP2-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CDP2-arm.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
-0xe0 0x6a 0x0c 0xfe
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS-arm.txt (removed)
@@ -1,9 +0,0 @@
-# CPS: various encodings that are ambiguous with other instructions
-
-# RUN: echo "0x9f 0xff 0x4e 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x80 0x80 0x2c 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0xce 0x3f 0x28 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x80 0x00 0x20 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0xa0 0x00 0x00 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# invalid imod value (0b01)
-0xc0 0x67 0x4 0xf1
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# invalid (imod, M, iflags) combination
-0x93 0x00 0x02 0xf1
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt (removed)
@@ -1,5 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# CBZ / CBNZ not allowed in IT block.
-
-0xdb 0xbf 0x42 0xbb
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt (removed)
@@ -1,7 +0,0 @@
-# CHECK-UNPRED: potentially undefined instruction encoding
-# CHECK-UNDEF: invalid instruction encoding
-
-# RUN: echo "0xff 0xbf 0x6b 0x80 0x00 0x75" | llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK-UNPRED
-
-# mask = 0
-# RUN: echo "0x50 0xbf 0x00 0x00" | llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK-UNDEF
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=0 Name=PHI Format=(42)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
-0x92 0xb4 0x1f 0xdc
-
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt (removed)
@@ -1,5 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# Writeback is not allowed is Rn is in the target register list.
-
-0xb4 0xe8 0x34 0x04
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR-thumb.txt (removed)
@@ -1,10 +0,0 @@
-# invalid LDRSHs Rt=PC
-# RUN: echo "0x30 0xf9 0x00 0xf0" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid LDRSHi8 Rt=PC
-# RUN: echo "0x30 0xf9 0x00 0xfc" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid LDRSHi12 Rt=PC
-# RUN: echo "0xb0 0xf9 0x00 0xf0" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if wback && (n == 15 || n == t) then UNPREDICTABLE
-0x05 0x70 0xd7 0xe6
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt (removed)
@@ -1,13 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined"
-
-# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.66 LDRD (immediate)
-# if Rn = '1111' then SEE LDRD (literal)
-# A8.6.67 LDRD (literal)
-# Inst{21} = 0
-0xff 0xe9 0x0 0xeb
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# LDR_PRE/POST has encoding Inst{4} = 0.
-0xde 0x69 0x18 0x46
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if m == 15 then UNPREDICTABLE
-0x8f 0x60 0xb7 0xe7
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# LDR (register) has encoding Inst{4} = 0.
-0xba 0xae 0x9f 0x57
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-MCR-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-MCR-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-MCR-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-MCR-arm.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C
-0x1b 0x1b 0xa0 0x2e
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if d == 15 then UNPREDICTABLE
-0x00 0xf0 0x41 0xe3
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt (removed)
@@ -1,13 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=0 Name=PHI Format=(42)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
-# The instruction is UNPREDICTABLE, and is not a valid intruction.
-#
-# See also
-# A8.6.97 MOV (register)
-0x2 0xd0 0xbc 0xf1
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt (removed)
@@ -1,17 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=0 Name=PHI Format=(42)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
-# The instruction is UNPREDICTABLE, and is not a valid intruction.
-#
-# See also
-# A8.6.88 LSL (immediate)
-# A8.6.98 MOV (shifted register), and
-# I.1 Instruction encoding diagrams and pseudocode
-0x2 0xd1 0xbc 0xf1
-
-
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
-0x00 0x1a 0x50 0xfc
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt (removed)
@@ -1,12 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
-# The hints instructions have more specific encodings, so if mask == 0,
-# we should reject this as an invalid instruction.
-0xa7 0xf1 0x20 0x3
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt (removed)
@@ -1,9 +0,0 @@
-# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
-
-# VMOV
-# RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VDUP
-# RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction
-# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
-0x32 0xb1 0x99 0xf8
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if d == 15 || n == 15 then UNPREDICTABLE;
-0x5f 0x54 0xa7 0xe7
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.167
-# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
-0x1b 0x68 0xf 0x97
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt (removed)
@@ -1,17 +0,0 @@
-# Opcode=0 Name=PHI Format=(42)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-# Unknown format
-#
-# B6.1.10 SRS
-# Inst{19-8} = 0xd05
-# Inst{7-5} = 0b000
-# RUN: echo "0x83 0x1c 0xc5 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# RUN: echo "0x00 0x00 0x20 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0xff 0xff 0xaf 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x13 0x00 0xa0 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if BitCount(registers) < 1 then UNPREDICTABLE
-0x00 0xc7
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-STR-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-STR-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-STR-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-STR-thumb.txt (removed)
@@ -1,37 +0,0 @@
-# invalid STRi12 Rn=PC
-# RUN: echo "0xcf 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRi8 Rn=PC
-# RUN: echo "0x4f 0xf8 0x00 0x0c" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRs Rn=PC
-# RUN: echo "0x4f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRBi12 Rn=PC
-# RUN: echo "0x0f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRBi8 Rn=PC
-# RUN: echo "0x0f 0xf8 0x00 0x0c" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRBs Rn=PC
-# RUN: echo "0x0f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRHi12 Rn=PC
-# RUN: echo "0xaf 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRHi8 Rn=PC
-# RUN: echo "0x2f 0xf8 0x00 0x0c" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRHs Rn=PC
-# RUN: echo "0x2f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRBT Rn=PC
-# RUN: echo "0x0f 0xf8 0x00 0x0e" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRHT Rn=PC
-# RUN: echo "0x2f 0xf8 0x00 0x0e" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# invalid STRT Rn=PC
-# RUN: echo "0x4f 0xf8 0x00 0x0e" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.223 SXTB
-# if d == 15 || m == 15 then UNPREDICTABLE;
-0x75 0xf4 0xaf 0xe6
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.244 UMAAL
-# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
-0x98 0xbf 0x4f 0xf0
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt (removed)
@@ -1,8 +0,0 @@
-# A8.8.307: VCVT (between floating-point and fixed-point, AdvSIMD)
-# imm6=0b0xxxxx -> UNDEFINED
-
-# RUN: echo "0x1e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
-
-# RUN: echo "0x3e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt (removed)
@@ -1,5 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding"
-
-# invalid imm4 value (0b1xxx)
-# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
-0x8f 0xf9 0xf7 0xf2
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt (removed)
@@ -1,9 +0,0 @@
-# VFP instructions with invalid predicate bits (pred != 0b1110)
-
-# VABS
-# RUN: echo "0x40 0xde 0x00 0x0a" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VMLA
-# RUN: echo "0xf0 0xde 0xe0 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# 'a' == 1 and data_size == 8 is invalid
-0x3d 0x3c 0xa0 0xf4
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0xa0 0xf9 0x10 0x08
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.315 VLD3 (single 3-element structure to all lanes)
-# The a bit must be encoded as 0.
-0xa2 0xf9 0x92 0x2e
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0xa0 0xf9 0xc0 0x0f
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0xa0 0xf9 0x30 0x0b
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# core registers out of range
-0xa5 0xba 0x72 0xed
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt (removed)
@@ -1,62 +0,0 @@
-# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
-# RUN: echo "0xaf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
-# RUN: echo "0xbf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
-# RUN: echo "0xbf 0x8a 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
-# RUN: echo "0xaf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
-# RUN: echo "0xbf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
-# RUN: echo "0x4f 0xa8 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
-# RUN: echo "0x4f 0xa9 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST3 multi-element, size = 0b11 -> undefined
-# RUN: echo "0xbf 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST3 multi-element, align = 0b10 -> undefined
-# RUN: echo "0x6f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST3 multi-element, align = 0b11 -> undefined
-# RUN: echo "0x7f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST4 multi-element, size = 0b11 -> undefined
-# RUN: echo "0xcf 0x50 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD1 multi-element, type=0b1010 align=0b11
-# RUN: echo "0x24 0xf9 0xbf 0x8a" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD1 multi-element type=0b0111 align=0b1x
-# RUN: echo "0x24 0xf9 0xbf 0x87" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD1 multi-element type=0b0010 align=0b1x
-# RUN: echo "0x24 0xf9 0xbf 0x86" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD2 multi-element size=0b11
-# RUN: echo "0x60 0xf9 0xcf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD2 multi-element type=0b1111 align=0b11
-# RUN: echo "0x60 0xf9 0xbf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD2 multi-element type=0b1001 align=0b11
-# RUN: echo "0x60 0xf9 0xbf 0x09" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD3 multi-element size=0b11
-# RUN: echo "0x60 0xf9 0x7f 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD3 multi-element align=0b1x
-# RUN: echo "0x60 0xf9 0xcf 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD4 multi-element size=0b11
-# RUN: echo "0x60 0xf9 0xcd 0x11" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
-
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt (removed)
@@ -1,7 +0,0 @@
-# VMOV cmode=0b1111 op=1
-# RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VMOV cmode=0b1111 op=1
-# RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# Qm -> bit[0] == 0, otherwise UNDEFINED
-0xdb 0xe0 0x40 0xf2
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0x80 0xf9 0x10 0x08
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt (removed)
@@ -1,13 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.391 VST1 (multiple single elements)
-# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128]
-# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list>
-# contains two or four registers. rdar://11220250
-0x00 0xf9 0x2f 0x06
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt (removed)
@@ -1,18 +0,0 @@
-# Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.393 VST2 (multiple 2-element structures)
-# type == '1001' and align == '11' ==> UNDEFINED
-# RUN: echo "0xb3 0x09 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# size == '11' ==> UNDEFINED
-# RUN: echo "0xc3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# type == '1000' and align == '11' ==> UNDEFINED
-# RUN: echo "0xb3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
-
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt (removed)
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0x80 0xf9 0x30 0x0b
-# CHECK: invalid instruction encoding
Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt?rev=186661&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt Fri Jul 19 05:05:04 2013
@@ -0,0 +1,510 @@
+# RUN: llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s
+
+# This file is checking ARMv7 encodings which are globally invalid, usually due
+# to the constraints of the instructions not being met. For example invalid
+# combinations of registers.
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for bfi
+#------------------------------------------------------------------------------
+
+# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == 15 then UNPREDICTABLE;
+[0x16 0xf0 0xcf 0xe7]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x16 0xf0 0xcf 0xe7]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for cdp2
+#------------------------------------------------------------------------------
+
+[0xe0 0x6a 0x0c 0xfe]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xe0 0x6a 0x0c 0xfe]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for cps*
+#------------------------------------------------------------------------------
+
+# invalid imod value (0b01)
+[0xc0 0x67 0x4 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xc0 0x67 0x4 0xf1]
+
+# invalid (imod, M, iflags) combination
+[0x93 0x00 0x02 0xf1]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x93 0x00 0x02 0xf1]
+
+# CPS: various encodings that are ambiguous with other instructions
+[0x9f 0xff 0x4e 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x9f 0xff 0x4e 0xf1]
+
+[0x80 0x80 0x2c 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x80 0x80 0x2c 0xf1]
+
+[0xce 0x3f 0x28 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xce 0x3f 0x28 0xf1]
+
+[0x80 0x00 0x20 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x80 0x00 0x20 0xf1]
+
+[0xa0 0x00 0x00 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa0 0x00 0x00 0xf1]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding space for hint instructions
+#------------------------------------------------------------------------------
+
+[0x05 0xf0 0x20 0xe3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x05 0xf0 0x20 0xe3]
+
+[0x41 0xf0 0x20 0xe3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x41 0xf0 0x20 0xe3]
+
+# FIXME: is it "dbg #14" or not????
+[0xfe 0xf0 0x20 0xe3]
+# CHCK: invalid instruction encoding
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldc
+#------------------------------------------------------------------------------
+
+# Opcode=0 Name=PHI Format=(42)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
+
+[0x92 0xb4 0x1f 0xdc]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x92 0xb4 0x1f 0xdc]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldm
+#------------------------------------------------------------------------------
+
+# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction
+# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
+
+[0x32 0xb1 0x99 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x32 0xb1 0x99 0xf8]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldr
+#------------------------------------------------------------------------------
+
+# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if m == 15 then UNPREDICTABLE
+
+[0x8f 0x60 0xb7 0xe7]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x8f 0x60 0xb7 0xe7]
+
+# LDR (register) has encoding Inst{4} = 0.
+[0xba 0xae 0x9f 0x57]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xba 0xae 0x9f 0x57]
+
+# LDR_PRE/POST has encoding Inst{4} = 0.
+[0xde 0x69 0x18 0x46]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xde 0x69 0x18 0x46]
+
+# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if wback && (n == 15 || n == t) then UNPREDICTABLE
+[0x05 0x70 0xd7 0xe6]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x05 0x70 0xd7 0xe6]
+
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for mcr
+#------------------------------------------------------------------------------
+
+# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C
+
+[0x1b 0x1b 0xa0 0x2e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x1b 0x1b 0xa0 0x2e]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for mov/lsl
+#------------------------------------------------------------------------------
+
+# Opcode=0 Name=PHI Format=(42)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
+# The instruction is UNPREDICTABLE, and is not a valid intruction.
+#
+# See also
+# A8.6.88 LSL (immediate)
+# A8.6.98 MOV (shifted register), and
+# I.1 Instruction encoding diagrams and pseudocode
+
+[0x2 0xd1 0xbc 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2 0xd1 0xbc 0xf1]
+
+
+# Opcode=0 Name=PHI Format=(42)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
+# The instruction is UNPREDICTABLE, and is not a valid intruction.
+#
+# See also
+# A8.6.97 MOV (register)
+
+[0x2 0xd0 0xbc 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2 0xd0 0xbc 0xf1]
+
+# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# A8.6.89 LSL (register): Inst{7-4} = 0b0001
+[0x93 0x42 0xa0 0xd1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x93 0x42 0xa0 0xd1]
+
+# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == 15 then UNPREDICTABLE
+[0x00 0xf0 0x41 0xe3]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x00 0xf0 0x41 0xe3]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for mrrc2
+#------------------------------------------------------------------------------
+
+[0x00 0x1a 0x50 0xfc]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0x1a 0x50 0xfc]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for msr (imm)
+#------------------------------------------------------------------------------
+
+# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
+# The hints instructions have more specific encodings, so if mask == 0,
+# we should reject this as an invalid instruction.
+
+[0xa7 0xf1 0x20 0x3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa7 0xf1 0x20 0x3]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for sbfx
+#------------------------------------------------------------------------------
+
+# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == 15 || n == 15 then UNPREDICTABLE;
+
+[0x5f 0x54 0xa7 0xe7]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x5f 0x54 0xa7 0xe7]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for smlad
+#------------------------------------------------------------------------------
+
+# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.167
+# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
+
+[0x1b 0x68 0xf 0x97]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x1b 0x68 0xf 0x97]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for srs
+#------------------------------------------------------------------------------
+
+# Opcode=0 Name=PHI Format=(42)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# Unknown format
+#
+# B6.1.10 SRS
+# Inst{19-8} = 0xd05
+# Inst{7-5} = 0b000
+
+[0x83 0x1c 0xc5 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x83 0x1c 0xc5 0xf8]
+
+[0x00 0x00 0x20 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0x00 0x20 0xf8]
+
+[0xff 0xff 0xaf 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xff 0xff 0xaf 0xf8]
+
+[0x13 0x00 0xa0 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x13 0x00 0xa0 0xf8]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for sxtb
+#------------------------------------------------------------------------------
+
+# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.223 SXTB
+# if d == 15 || m == 15 then UNPREDICTABLE;
+
+[0x75 0xf4 0xaf 0xe6]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x75 0xf4 0xaf 0xe6]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON umaal
+#------------------------------------------------------------------------------
+
+# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.244 UMAAL
+# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
+[0x98 0xbf 0x4f 0xf0]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x98 0xbf 0x4f 0xf0]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vcvt (float <-> fixed)
+#------------------------------------------------------------------------------
+
+# imm6=0b0xxxxx -> UNDEFINED
+[0x1e 0xcf 0x92 0xf3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x1e 0xcf 0x92 0xf3]
+
+[0x3e 0xcf 0x92 0xf3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x3e 0xcf 0x92 0xf3]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vext
+#------------------------------------------------------------------------------
+
+# invalid imm4 value (0b1xxx)
+# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
+[0x8f 0xf9 0xf7 0xf2]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x8f 0xf9 0xf7 0xf2]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vldmsdb
+#------------------------------------------------------------------------------
+
+# core registers out of range
+[0xa5 0xba 0x72 0xed]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xa5 0xba 0x72 0xed]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vmov
+#------------------------------------------------------------------------------
+
+# VMOV cmode=0b1111 op=1 is UNDEFINED
+[0x70 0xef 0xc7 0xf3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x70 0xef 0xc7 0xf3]
+
+# VMOV cmode=0b1111 op=1 is UNDEFINED
+[0x30 0x0f 0x80 0xf3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x30 0x0f 0x80 0xf3]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vqadd
+#------------------------------------------------------------------------------
+
+# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# Qm -> bit[0] == 0, otherwise UNDEFINED
+[0xdb 0xe0 0x40 0xf2]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xdb 0xe0 0x40 0xf2]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vld/vst
+#------------------------------------------------------------------------------
+
+# A8.6.393 VST2 (multiple 2-element structures)
+[0xb3 0x09 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xb3 0x09 0x03 0xf4]
+
+# size == '11' ==> UNDEFINED
+[0xc3 0x08 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xc3 0x08 0x03 0xf4]
+
+# type == '1000' and align == '11' ==> UNDEFINED
+[0xb3 0x08 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xb3 0x08 0x03 0xf4]
+
+# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
+[0xaf 0xb7 0x07 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xb7 0x07 0xf4]
+
+# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
+[0xbf 0xb7 0x07 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xbf 0xb7 0x07 0xf4]
+
+# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
+[0xbf 0x8a 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xbf 0x8a 0x03 0xf4]
+
+# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
+[0xaf 0xb6 0x07 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xb6 0x07 0xf4]
+
+# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
+[0xbf 0xb6 0x07 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xbf 0xb6 0x07 0xf4]
+
+# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
+[0x4f 0xa8 0x07 0xf7]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xa8 0x07 0xf7]
+
+# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
+[0x4f 0xa9 0x07 0xf7]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xa9 0x07 0xf7]
+
+# VST3 multi-element, size = 0b11 -> undefined
+[0xbf 0xa4 0x0b 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xbf 0xa4 0x0b 0xf4]
+
+# VST3 multi-element, align = 0b10 -> undefined
+[0x6f 0xa4 0x0b 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x6f 0xa4 0x0b 0xf4]
+
+# VST3 multi-element, align = 0b11 -> undefined
+[0x7f 0xa4 0x0b 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x7f 0xa4 0x0b 0xf4]
+
+# VST4 multi-element, size = 0b11 -> undefined
+[0xcf 0x50 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xcf 0x50 0x03 0xf4]
+
+
+# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# 'a' == 1 and data_size == 8 is invalid
+[0x3d 0x3c 0xa0 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4]
Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt?rev=186661&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt Fri Jul 19 05:05:04 2013
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -disassemble -triple armv7 -show-encoding < %s 2>&1 | FileCheck %s
+
+# This file is checking encodings that are valid on some triples, but not on the
+# ARMv7 triple, probably because the relevant instruction is v8, though there
+# could be other reasons.
+
+# Would be vcvtt.f64.f16 d3, s1
+[0xe0 0x3b 0xb2 0xee]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xe0 0x3b 0xb2 0xee]
+
+# Would be vcvtb.f16.f64 s4, d1
+[0x41 0x2b 0xb3 0xee]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x41 0x2b 0xb3 0xee]
+
+# Would be vcvtblt.f16.f64 s4, d1
+[0x41 0x2b 0xb3 0xbe]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x41 0x2b 0xb3 0xbe]
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-arm.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-arm.txt (removed)
@@ -1,13 +0,0 @@
-# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s 2>&1 | FileCheck %s
-
-#------------------------------------------------------------------------------
-# Undefined encoding space for hint instructions
-#------------------------------------------------------------------------------
-
-0x05 0xf0 0x20 0xe3
-# CHECK: invalid instruction encoding
-0x41 0xf0 0x20 0xe3
-# CHECK: invalid instruction encoding
-0xfe 0xf0 0x20 0xe3
-# CHECK: invalid instruction encoding
-
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-hint-thumb.txt (removed)
@@ -1,8 +0,0 @@
-# RUN: llvm-mc -triple=thumbv7 -disassemble -show-encoding < %s 2>&1 | FileCheck %s
-
-#------------------------------------------------------------------------------
-# Undefined encoding space for hint instructions
-#------------------------------------------------------------------------------
-
-0xaf 0xf3 0x05 0x80
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.16 B
-# if cond<3:1> == '111' then SEE "Related Encodings"
-0xaf 0xf7 0x44 0x8b
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# The unpriviledged Load/Store cannot have SP or PC as Rt.
-0x10 0xf8 0x3 0xfe
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-# XFAIL: *
-
-# Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 1| 0: 0: 1: 0| 1: 0: 0: 0| 1: 0: 0: 0| 0: 1: 1: 1| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if t == t2 then UNPREDICTABLE
-0xd2 0xe8 0x7f 0x88
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if Rt = '1111' then SEE "Unallocated memory hints"
-0xb3 0xf9 0xdf 0xf8
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"
-0x35 0xf9 0x00 0xfc
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt (removed)
@@ -1,5 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# SP and PC are not allowed in the register list on STM instructions in Thumb2.
-
-0x2d 0xe9 0xf7 0xb6
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined"
-
-# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 0| 0: 1: 0: 0| 0: 1: 0: 0| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if wback && (n == t || n == t2) then UNPREDICTABLE
-0xe4 0xe9 0x02 0x46
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt (removed)
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-# XFAIL: *
-
-# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if d == n || d == t then UNPREDICTABLE
-0xc2 0xe8 0x42 0x8f
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if d == n || d == t || d == t2 then UNPREDICTABLE
-mc-input.txt:1:1: warning: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if Rn == '1111' then UNDEFINED
-0x4f 0xf8 0xff 0xeb
Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt?rev=186661&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt Fri Jul 19 05:05:04 2013
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s
+# XFAIL: *
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldrexd/strexd
+#------------------------------------------------------------------------------
+
+# FIXME: "ldrexd r8, r8, [r2]"
+# Rt == Rt2 is UNPREDICTABLE
+
+[0xd2 0xe8 0x7f 0x88]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xd2 0xe8 0x7f 0x88]
+
+# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == n || d == t then UNPREDICTABLE
+
+[0xc2 0xe8 0x42 0x8f]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xc2 0xe8 0x42 0x8f]
+
+# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == n || d == t || d == t2 then UNPREDICTABLE
+
+# FIXME: should be unpredictable since it's "strexd r8, r7, r8, [r2]"
+[0xc2 0xe8 0x78 0x78]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xc2 0xe8 0x78 0x78]
Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt?rev=186661&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt Fri Jul 19 05:05:04 2013
@@ -0,0 +1,404 @@
+# RUN: llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s
+
+# This file is checking Thumbv7 encodings which are globally invalid, usually due
+# to the constraints of the instructions not being met. For example invalid
+# combinations of registers.
+
+#------------------------------------------------------------------------------
+# Undefined encoding for b.cc
+#------------------------------------------------------------------------------
+
+# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.16 B
+# if cond<3:1> == '111' then SEE "Related Encodings"
+
+[0xaf 0xf7 0x44 0x8b]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xf7 0x44 0x8b]
+
+# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if cond = '1110' then UNDEFINED
+[0x6f 0xde]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x6f 0xde]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding space for hint instructions
+#------------------------------------------------------------------------------
+
+[0xaf 0xf3 0x05 0x80]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xf3 0x05 0x80]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding for it
+#------------------------------------------------------------------------------
+
+[0xff 0xbf 0x6b 0x80 0x00 0x75]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75]
+
+# mask = 0
+[0x50 0xbf 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x50 0xbf 0x00 0x00]
+
+# Two warnings from this block since there are two instructions in there
+[0xdb 0xbf 0x42 0xbb]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]
+
+#------------------------------------------------------------------------------
+# Undefined encoding for ldm
+#------------------------------------------------------------------------------
+
+# Writeback is not allowed is Rn is in the target register list.
+[0xb4 0xe8 0x34 0x04]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xb4 0xe8 0x34 0x04]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding for ldrd
+#------------------------------------------------------------------------------
+
+# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.66 LDRD (immediate)
+# if Rn = '1111' then SEE LDRD (literal)
+# A8.6.67 LDRD (literal)
+# Inst{21} = 0
+
+[0xff 0xe9 0x0 0xeb]
+# CHECK: potentially undefined
+# CHECK-NEXT: [0xff 0xe9 0x0 0xeb]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldrbt
+#------------------------------------------------------------------------------
+
+# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# The unpriviledged Load/Store cannot have SP or PC as Rt.
+[0x10 0xf8 0x3 0xfe]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x10 0xf8 0x3 0xfe]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldrsh
+#------------------------------------------------------------------------------
+
+# invalid LDRSHs Rt=PC
+[0x30 0xf9 0x00 0xf0]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x30 0xf9 0x00 0xf0]
+
+# invalid LDRSHi8 Rt=PC
+[0x30 0xf9 0x00 0xfc]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x30 0xf9 0x00 0xfc]
+
+# invalid LDRSHi12 Rt=PC
+[0xb0 0xf9 0x00 0xf0]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xb0 0xf9 0x00 0xf0]
+
+# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"
+[0x35 0xf9 0x00 0xfc]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x35 0xf9 0x00 0xfc]
+
+# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if Rt = '1111' then SEE "Unallocated memory hints"
+[0xb3 0xf9 0xdf 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding for push
+#------------------------------------------------------------------------------
+
+# SP and PC are not allowed in the register list on STM instructions in Thumb2.
+[0x2d 0xe9 0xf7 0xb6]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding for stmia
+#------------------------------------------------------------------------------
+
+# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if BitCount(registers) < 1 then UNPREDICTABLE
+[0x00 0xc7]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0xc7]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for str
+#------------------------------------------------------------------------------
+
+# invalid STRi12 Rn=PC
+[0xcf 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xcf 0xf8 0x00 0x00]
+
+# invalid STRi8 Rn=PC
+[0x4f 0xf8 0x00 0x0c]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xf8 0x00 0x0c]
+
+# invalid STRs Rn=PC
+[0x4f 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xf8 0x00 0x00]
+
+# invalid STRBi12 Rn=PC
+[0x0f 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x0f 0xf8 0x00 0x00]
+
+# invalid STRBi8 Rn=PC
+[0x0f 0xf8 0x00 0x0c]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x0f 0xf8 0x00 0x0c]
+
+# invalid STRBs Rn=PC
+[0x0f 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x0f 0xf8 0x00 0x00]
+
+# invalid STRHi12 Rn=PC
+[0xaf 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xf8 0x00 0x00]
+
+# invalid STRHi8 Rn=PC
+[0x2f 0xf8 0x00 0x0c]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2f 0xf8 0x00 0x0c]
+
+# invalid STRHs Rn=PC
+[0x2f 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2f 0xf8 0x00 0x00]
+
+# invalid STRBT Rn=PC
+[0x0f 0xf8 0x00 0x0e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x0f 0xf8 0x00 0x0e]
+
+# invalid STRHT Rn=PC
+[0x2f 0xf8 0x00 0x0e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2f 0xf8 0x00 0x0e]
+
+# invalid STRT Rn=PC
+[0x4f 0xf8 0x00 0x0e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xf8 0x00 0x0e]
+
+# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if Rn == '1111' then UNDEFINED
+
+[0x4f 0xf8 0xff 0xeb]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xf8 0xff 0xeb]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for strd
+#------------------------------------------------------------------------------
+
+# Rt == Rn is UNPREDICTABLE
+[0xe4 0xe9 0x02 0x46]
+# CHECK: warning: potentially undefined instruction encoding
+# CHECK-NEXT: [0xe4 0xe9 0x02 0x46]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON/VFP instructions with invalid predicate bits
+#------------------------------------------------------------------------------
+
+# VABS
+[0x40 0xde 0x00 0x0a]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x40 0xde 0x00 0x0a]
+
+
+# VMLA
+[0xf0 0xde 0xe0 0x0b]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xf0 0xde 0xe0 0x0b]
+
+# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
+
+# VMOV
+[0x00 0xde 0x10 0x0b]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0xde 0x10 0x0b]
+
+# VDUP
+[0xff 0xde 0xf0 0xfb]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xff 0xde 0xf0 0xfb]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vld instructions
+#------------------------------------------------------------------------------
+
+# size = '00' and index_align == '0001' so UNDEFINED
+[0xa0 0xf9 0x10 0x08]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa0 0xf9 0x10 0x08]
+
+
+# vld3
+
+# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.315 VLD3 (single 3-element structure to all lanes)
+# The a bit must be encoded as 0.
+
+[0xa2 0xf9 0x92 0x2e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa2 0xf9 0x92 0x2e]
+
+
+# Some vld4 ones
+# size == '11' and a == '0' so UNDEFINED
+[0xa0 0xf9 0xc0 0x0f]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f]
+
+[0xa0 0xf9 0x30 0x0b]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa0 0xf9 0x30 0x0b]
+
+
+# VLD1 multi-element, type=0b1010 align=0b11
+[0x24 0xf9 0xbf 0x8a]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x24 0xf9 0xbf 0x8a]
+
+# VLD1 multi-element type=0b0111 align=0b1x
+[0x24 0xf9 0xbf 0x87]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x24 0xf9 0xbf 0x87]
+
+# VLD1 multi-element type=0b0010 align=0b1x
+[0x24 0xf9 0xbf 0x86]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x24 0xf9 0xbf 0x86]
+
+# VLD2 multi-element size=0b11
+[0x60 0xf9 0xcf 0x08]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xcf 0x08]
+
+# VLD2 multi-element type=0b1111 align=0b11
+[0x60 0xf9 0xbf 0x08]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xbf 0x08]
+
+# VLD2 multi-element type=0b1001 align=0b11
+[0x60 0xf9 0xbf 0x09]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xbf 0x09]
+
+# VLD3 multi-element size=0b11
+[0x60 0xf9 0x7f 0x04]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0x7f 0x04]
+
+# VLD3 multi-element align=0b1x
+[0x60 0xf9 0xcf 0x04]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xcf 0x04]
+
+# VLD4 multi-element size=0b11
+[0x60 0xf9 0xcd 0x11]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xcd 0x11]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vst1
+#------------------------------------------------------------------------------
+
+# size == '10' and index_align == '0001' so UNDEFINED
+[0x80 0xf9 0x10 0x08]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x80 0xf9 0x10 0x08]
+
+# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.391 VST1 (multiple single elements)
+# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128]
+# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list>
+# contains two or four registers. rdar://11220250
+[0x00 0xf9 0x2f 0x06]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0xf9 0x2f 0x06]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vst4
+#------------------------------------------------------------------------------
+
+[0x80 0xf9 0x30 0x0b]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x80 0xf9 0x30 0x0b]
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-v8fp.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-v8fp.txt?rev=186660&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-v8fp.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-v8fp.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc -disassemble -triple armv7 -show-encoding < %s | FileCheck %s
-
-0xe0 0x3b 0xb2 0xee
-# CHECK-NOT: vcvtt.f64.f16 d3, s1
-
-0x41 0x2b 0xb3 0xee
-# CHECK-NOT: vcvtb.f16.f64 s4, d1
-
-0x41 0x2b 0xb3 0xbe
-# CHECK-NOT: vcvtblt.f16.f64 s4, d1
Modified: llvm/trunk/tools/llvm-mc/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.cpp?rev=186661&r1=186660&r2=186661&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/Disassembler.cpp (original)
+++ llvm/trunk/tools/llvm-mc/Disassembler.cpp Fri Jul 19 05:05:04 2013
@@ -51,7 +51,7 @@ public:
static bool PrintInsts(const MCDisassembler &DisAsm,
const ByteArrayTy &Bytes,
SourceMgr &SM, raw_ostream &Out,
- MCStreamer &Streamer) {
+ MCStreamer &Streamer, bool InAtomicBlock) {
// Wrap the vector in a MemoryObject.
VectorMemoryObject memoryObject(Bytes);
@@ -70,8 +70,13 @@ static bool PrintInsts(const MCDisassemb
SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second),
SourceMgr::DK_Warning,
"invalid instruction encoding");
+ // Don't try to resynchronise the stream in a block
+ if (InAtomicBlock)
+ return true;
+
if (Size == 0)
Size = 1; // skip illegible bytes
+
break;
case MCDisassembler::SoftFail:
@@ -89,14 +94,11 @@ static bool PrintInsts(const MCDisassemb
return false;
}
-static bool ByteArrayFromString(ByteArrayTy &ByteArray,
- StringRef &Str,
- SourceMgr &SM) {
- while (!Str.empty()) {
- // Strip horizontal whitespace.
- if (size_t Pos = Str.find_first_not_of(" \t\r")) {
+static bool SkipToToken(StringRef &Str) {
+ while (!Str.empty() && Str.find_first_not_of(" \t\r\n#,") != 0) {
+ // Strip horizontal whitespace and commas.
+ if (size_t Pos = Str.find_first_not_of(" \t\r,")) {
Str = Str.substr(Pos);
- continue;
}
// If this is the end of a line or start of a comment, remove the rest of
@@ -113,9 +115,22 @@ static bool ByteArrayFromString(ByteArra
}
continue;
}
+ }
+
+ return !Str.empty();
+}
+
+
+static bool ByteArrayFromString(ByteArrayTy &ByteArray,
+ StringRef &Str,
+ SourceMgr &SM) {
+ while (SkipToToken(Str)) {
+ // Handled by higher level
+ if (Str[0] == '[' || Str[0] == ']')
+ return false;
// Get the current token.
- size_t Next = Str.find_first_of(" \t\n\r#");
+ size_t Next = Str.find_first_of(" \t\n\r,#[]");
StringRef Value = Str.substr(0, Next);
// Convert to a byte and add to the byte vector.
@@ -157,11 +172,44 @@ int Disassembler::disassemble(const Targ
// Convert the input to a vector for disassembly.
ByteArrayTy ByteArray;
StringRef Str = Buffer.getBuffer();
+ bool InAtomicBlock = false;
+
+ while (SkipToToken(Str)) {
+ ByteArray.clear();
+
+ if (Str[0] == '[') {
+ if (InAtomicBlock) {
+ SM.PrintMessage(SMLoc::getFromPointer(Str.data()), SourceMgr::DK_Error,
+ "nested atomic blocks make no sense");
+ ErrorOccurred = true;
+ }
+ InAtomicBlock = true;
+ Str = Str.drop_front();
+ continue;
+ } else if (Str[0] == ']') {
+ if (!InAtomicBlock) {
+ SM.PrintMessage(SMLoc::getFromPointer(Str.data()), SourceMgr::DK_Error,
+ "attempt to close atomic block without opening");
+ ErrorOccurred = true;
+ }
+ InAtomicBlock = false;
+ Str = Str.drop_front();
+ continue;
+ }
- ErrorOccurred |= ByteArrayFromString(ByteArray, Str, SM);
+ // It's a real token, get the bytes and emit them
+ ErrorOccurred |= ByteArrayFromString(ByteArray, Str, SM);
- if (!ByteArray.empty())
- ErrorOccurred |= PrintInsts(*DisAsm, ByteArray, SM, Out, Streamer);
+ if (!ByteArray.empty())
+ ErrorOccurred |= PrintInsts(*DisAsm, ByteArray, SM, Out, Streamer,
+ InAtomicBlock);
+ }
+
+ if (InAtomicBlock) {
+ SM.PrintMessage(SMLoc::getFromPointer(Str.data()), SourceMgr::DK_Error,
+ "unclosed atomic block");
+ ErrorOccurred = true;
+ }
return ErrorOccurred;
}
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