[llvm] r186250 - Convert a couple of grep tests to FileCheck.
Benjamin Kramer
benny.kra at googlemail.com
Sat Jul 13 10:30:25 PDT 2013
Author: d0k
Date: Sat Jul 13 12:30:25 2013
New Revision: 186250
URL: http://llvm.org/viewvc/llvm-project?rev=186250&view=rev
Log:
Convert a couple of grep tests to FileCheck.
Modified:
llvm/trunk/test/CodeGen/X86/mmx-arg-passing.ll
llvm/trunk/test/CodeGen/X86/mmx-shift.ll
llvm/trunk/test/CodeGen/X86/narrow_op-1.ll
llvm/trunk/test/CodeGen/X86/private.ll
llvm/trunk/test/CodeGen/X86/rodata-relocs.ll
llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll
Modified: llvm/trunk/test/CodeGen/X86/mmx-arg-passing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-arg-passing.ll?rev=186250&r1=186249&r2=186250&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-arg-passing.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mmx-arg-passing.ll Sat Jul 13 12:30:25 2013
@@ -1,8 +1,5 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep mm0 | count 1
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep esp | count 2
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep xmm0
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep rdi
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | not grep movups
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | FileCheck %s -check-prefix=X86-32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s -check-prefix=X86-64
;
; On Darwin x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
; On Darwin x86-32, v1i64 values are passed in memory. In this example, they
@@ -15,6 +12,13 @@
define void @t1(x86_mmx %v1) nounwind {
store x86_mmx %v1, x86_mmx* @u1, align 8
ret void
+
+; X86-32: t1:
+; X86-32: movq %mm0
+
+; X86-64: t1:
+; X86-64: movdq2q %xmm0
+; X86-64: movq %mm0
}
@u2 = external global x86_mmx
@@ -23,5 +27,12 @@ define void @t2(<1 x i64> %v1) nounwind
%tmp = bitcast <1 x i64> %v1 to x86_mmx
store x86_mmx %tmp, x86_mmx* @u2, align 8
ret void
+
+; X86-32: t2:
+; X86-32: movl 4(%esp)
+; X86-32: movl 8(%esp)
+
+; X86-64: t2:
+; X86-64: movq %rdi
}
Modified: llvm/trunk/test/CodeGen/X86/mmx-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-shift.ll?rev=186250&r1=186249&r2=186250&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mmx-shift.ll Sat Jul 13 12:30:25 2013
@@ -1,7 +1,5 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx | grep psllq | grep 32
-; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psllq | grep 32
-; RUN: llc < %s -march=x86 -mattr=+mmx | grep psrad
-; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psrlw
+; RUN: llc < %s -march=x86 -mattr=+mmx | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | FileCheck %s
define i64 @t1(<1 x i64> %mm1) nounwind {
entry:
@@ -9,6 +7,9 @@ entry:
%tmp6 = tail call x86_mmx @llvm.x86.mmx.pslli.q( x86_mmx %tmp, i32 32 ) ; <x86_mmx> [#uses=1]
%retval1112 = bitcast x86_mmx %tmp6 to i64
ret i64 %retval1112
+
+; CHECK: t1:
+; CHECK: psllq $32
}
declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) nounwind readnone
@@ -18,6 +19,9 @@ entry:
%tmp7 = tail call x86_mmx @llvm.x86.mmx.psra.d( x86_mmx %mm1, x86_mmx %mm2 ) nounwind readnone ; <x86_mmx> [#uses=1]
%retval1112 = bitcast x86_mmx %tmp7 to i64
ret i64 %retval1112
+
+; CHECK: t2:
+; CHECK: psrad
}
declare x86_mmx @llvm.x86.mmx.psra.d(x86_mmx, x86_mmx) nounwind readnone
@@ -27,6 +31,9 @@ entry:
%tmp8 = tail call x86_mmx @llvm.x86.mmx.psrli.w( x86_mmx %mm1, i32 %bits ) nounwind readnone ; <x86_mmx> [#uses=1]
%retval1314 = bitcast x86_mmx %tmp8 to i64
ret i64 %retval1314
+
+; CHECK: t3:
+; CHECK: psrlw
}
declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32) nounwind readnone
Modified: llvm/trunk/test/CodeGen/X86/narrow_op-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/narrow_op-1.ll?rev=186250&r1=186249&r2=186250&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/narrow_op-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/narrow_op-1.ll Sat Jul 13 12:30:25 2013
@@ -1,7 +1,4 @@
-; RUN: llc < %s -march=x86-64 | grep orb | count 1
-; RUN: llc < %s -march=x86-64 | grep orb | grep 1
-; RUN: llc < %s -march=x86-64 | grep orl | count 1
-; RUN: llc < %s -march=x86-64 | grep orl | grep 16842752
+; RUN: llc < %s -march=x86-64 | FileCheck %s
%struct.bf = type { i64, i16, i16, i32 }
@bfi = common global %struct.bf zeroinitializer, align 16
@@ -12,6 +9,10 @@ entry:
%1 = or i32 %0, 65536
store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
ret void
+
+; CHECK: t1:
+; CHECK: orb $1
+; CHECK-NEXT: ret
}
define void @t2() nounwind optsize ssp {
@@ -20,4 +21,8 @@ entry:
%1 = or i32 %0, 16842752
store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
ret void
+
+; CHECK: t2:
+; CHECK: orl $16842752
+; CHECK-NEXT: ret
}
Modified: llvm/trunk/test/CodeGen/X86/private.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/private.ll?rev=186250&r1=186249&r2=186250&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/private.ll (original)
+++ llvm/trunk/test/CodeGen/X86/private.ll Sat Jul 13 12:30:25 2013
@@ -1,18 +1,22 @@
; Test to make sure that the 'private' is used correctly.
;
-; RUN: llc < %s -mtriple=x86_64-pc-linux | grep .Lfoo:
-; RUN: llc < %s -mtriple=x86_64-pc-linux | grep call.*\.Lfoo
-; RUN: llc < %s -mtriple=x86_64-pc-linux | grep .Lbaz:
-; RUN: llc < %s -mtriple=x86_64-pc-linux | grep movl.*\.Lbaz
+; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
define private void @foo() {
ret void
-}
- at baz = private global i32 4
+; CHECK: .Lfoo:
+}
define i32 @bar() {
call void @foo()
%1 = load i32* @baz, align 4
ret i32 %1
+
+; CHECK: bar:
+; CHECK: callq .Lfoo
+; CHECK: movl .Lbaz(%rip)
}
+
+ at baz = private global i32 4
+; CHECK: .Lbaz:
Modified: llvm/trunk/test/CodeGen/X86/rodata-relocs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rodata-relocs.ll?rev=186250&r1=186249&r2=186250&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/rodata-relocs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/rodata-relocs.ll Sat Jul 13 12:30:25 2013
@@ -1,13 +1,9 @@
-; RUN: llc < %s -relocation-model=static | grep rodata | count 3
-; RUN: llc < %s -relocation-model=static | grep -F "rodata.cst" | count 2
-; RUN: llc < %s -relocation-model=pic | grep rodata | count 2
-; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.ro" | count 2
-; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.ro.local" | count 1
-; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel" | count 4
-; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.local" | count 1
+; RUN: llc < %s -relocation-model=static | FileCheck %s -check-prefix=STATIC
+; RUN: llc < %s -relocation-model=pic | FileCheck %s -check-prefix=PIC
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
+
@a = internal unnamed_addr constant [2 x i32] [i32 1, i32 2]
@a1 = unnamed_addr constant [2 x i32] [i32 1, i32 2]
@e = internal unnamed_addr constant [2 x [2 x i32]] [[2 x i32] [i32 1, i32 2], [2 x i32] [i32 3, i32 4]], align 16
@@ -21,3 +17,30 @@ target triple = "x86_64-unknown-linux-gn
@p3 = internal global i8* bitcast([2 x i32]* @a to i8*)
@t3 = internal global i8* bitcast([2 x [2 x i32]]* @e to i8*)
+; STATIC: .section .rodata.cst8,"aM", at progbits,8
+; STATIC: a:
+; STATIC: a1:
+; STATIC: .section .rodata.cst16,"aM", at progbits,16
+; STATIC: e:
+; STATIC: e1:
+; STATIC: .section .rodata,"a", at progbits
+; STATIC: p:
+
+; PIC: .section .rodata.cst8,"aM", at progbits,8
+; PIC: a:
+; PIC: a1:
+; PIC: .section .rodata.cst16,"aM", at progbits,16
+; PIC: e:
+; PIC: e1:
+; PIC: .section .data.rel.ro.local,"aw", at progbits
+; PIC: p:
+; PIC: t:
+; PIC: .section .data.rel.ro,"aw", at progbits
+; PIC: p1:
+; PIC: t1:
+; PIC: .section .data.rel,"aw", at progbits
+; PIC: p2:
+; PIC: t2:
+; PIC: .section .data.rel.local,"aw", at progbits
+; PIC: p3:
+; PIC: t3:
Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll?rev=186250&r1=186249&r2=186250&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll Sat Jul 13 12:30:25 2013
@@ -1,14 +1,17 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2
-; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 2
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 3
-; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X86-32
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | FileCheck %s -check-prefix=X86-64
define <4 x i32> @t1(i32 %a) nounwind {
entry:
%tmp = insertelement <4 x i32> undef, i32 %a, i32 0
%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp, <4 x i32> < i32 4, i32 1, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
ret <4 x i32> %tmp6
+
+; X86-32: t1:
+; X86-32: movd 4(%esp), %xmm0
+
+; X86-64: t1:
+; X86-64: movd %e{{..}}, %xmm0
}
define <2 x i64> @t2(i64 %a) nounwind {
@@ -16,6 +19,12 @@ entry:
%tmp = insertelement <2 x i64> undef, i64 %a, i32 0
%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %tmp, <2 x i32> < i32 2, i32 1 > ; <<4 x i32>> [#uses=1]
ret <2 x i64> %tmp6
+
+; X86-32: t2:
+; X86-32: movq 4(%esp), %xmm0
+
+; X86-64: t2:
+; X86-64: movd %r{{..}}, %xmm0
}
define <2 x i64> @t3(<2 x i64>* %a) nounwind {
@@ -25,6 +34,13 @@ entry:
%tmp7 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp6, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
%tmp8 = bitcast <4 x i32> %tmp7 to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp8
+
+; X86-32: t3:
+; X86-32: movl 4(%esp)
+; X86-32: movq
+
+; X86-64: t3:
+; X86-64: movq ({{.*}}), %xmm0
}
define <2 x i64> @t4(<2 x i64> %a) nounwind {
@@ -33,10 +49,22 @@ entry:
%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp5, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
%tmp7 = bitcast <4 x i32> %tmp6 to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp7
+
+; X86-32: t4:
+; X86-32: movq %xmm0, %xmm0
+
+; X86-64: t4:
+; X86-64: movq {{.*}}, %xmm0
}
define <2 x i64> @t5(<2 x i64> %a) nounwind {
entry:
%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> < i32 2, i32 1 > ; <<4 x i32>> [#uses=1]
ret <2 x i64> %tmp6
+
+; X86-32: t5:
+; X86-32: movq %xmm0, %xmm0
+
+; X86-64: t5:
+; X86-64: movq {{.*}}, %xmm0
}
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