[PATCH] Fix ARM paired GPR COPY lowering

[JF Bastien]

Committed as r186226.


On Fri, Jul 12, 2013 at 2:43 PM, Eric Christopher <echristo at gmail.com>wrote:

> LGTM.
>
> -eric
>
> On Wed, Jul 10, 2013 at 10:21 AM, JF Bastien <jfb at google.com> wrote:
> > ARM paired GPR COPY was being lowered to two MOVr without CC. This
> > patch puts the CC back.
> >
> > My test is a reduction of the case where I encountered the issue, but
> > I'm not sure it's the best one ever (though 64-bit atomics do require
> > paired GPRs).
> >
> > The issue only occurs with selectionDAG, FastISel doesn't encounter it
> > so I didn't bother calling it.
> >
> >
> >
> >
> > diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp
> > b/lib/Target/ARM/ARMBaseInstrInfo.cpp
> > index 5283d7b..d670178 100644
> > --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
> > +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
> > @@ -745,6 +745,9 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock
> &MBB,
> >      if (Opc == ARM::VORRq)
> >        Mov.addReg(Src);
> >      Mov = AddDefaultPred(Mov);
> > +    // MOVr can set CC.
> > +    if (Opc == ARM::MOVr)
> > +      Mov = AddDefaultCC(Mov);
> >    }
> >    // Add implicit super-register defs and kills to the last instruction.
> >    Mov->addRegisterDefined(DestReg, TRI);
> > diff --git a/test/CodeGen/ARM/copy-paired-reg.ll
> > b/test/CodeGen/ARM/copy-paired-reg.ll
> > new file mode 100644
> > index 0000000..17a4461
> > --- /dev/null
> > +++ b/test/CodeGen/ARM/copy-paired-reg.ll
> > @@ -0,0 +1,17 @@
> > +; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs
> > +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -verify-machineinstrs
> > +
> > +define void @f() {
> > +  %a = alloca i8, i32 8, align 8
> > +  %b = alloca i8, i32 8, align 8
> > +
> > +  %c = bitcast i8* %a to i64*
> > +  %d = bitcast i8* %b to i64*
> > +
> > +  store atomic i64 0, i64* %c seq_cst, align 8
> > +  store atomic i64 0, i64* %d seq_cst, align 8
> > +
> > +  %e = load atomic i64* %d seq_cst, align 8
> > +
> > +  ret void
> > +}
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>
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