[llvm] r186070 - [SystemZ] Allow 8-bit operands to RISBG

[Richard Sandiford]

Author: rsandifo
Date: Thu Jul 11 03:37:13 2013
New Revision: 186070

URL: http://llvm.org/viewvc/llvm-project?rev=186070&view=rev
Log:
[SystemZ] Allow 8-bit operands to RISBG

RISBG has three 8-bit operands (I3, I4 and I5).  I'd originally
restricted all three to 6 bits, since that's the only range we intended
to use at the time.  However, the top bit of I4 acts as a "zero" flag for
RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co.
This patch therefore allows them to have the full 8-bit range.
I've left the fifth operand as a 6-bit value for now since the
upper 2 bits have no defined meaning.

Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
    llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
    llvm/trunk/test/MC/SystemZ/insn-bad.s
    llvm/trunk/test/MC/SystemZ/insn-good.s

Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=186070&r1=186069&r2=186070&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Thu Jul 11 03:37:13 2013
@@ -1020,8 +1020,7 @@ multiclass CmpSwapRSPair<string mnemonic
 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
                        RegisterOperand cls2>
   : InstRIEf<opcode, (outs cls1:$R1),
-             (ins cls1:$R1src, cls2:$R2,
-                  uimm8zx6:$I3, uimm8zx6:$I4, uimm8zx6:$I5),
+             (ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5),
              mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";

Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=186070&r1=186069&r2=186070&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Thu Jul 11 03:37:13 2013
@@ -4642,11 +4642,11 @@
 # CHECK: risbg %r0, %r0, 0, 0, 63
 0xec 0x00 0x00 0x00 0x3f 0x55
 
-# CHECK: risbg %r0, %r0, 0, 63, 0
-0xec 0x00 0x00 0x3f 0x00 0x55
+# CHECK: risbg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x55
 
-# CHECK: risbg %r0, %r0, 63, 0, 0
-0xec 0x00 0x3f 0x00 0x00 0x55
+# CHECK: risbg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x55
 
 # CHECK: risbg %r0, %r15, 0, 0, 0
 0xec 0x0f 0x00 0x00 0x00 0x55

Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=186070&r1=186069&r2=186070&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Thu Jul 11 03:37:13 2013
@@ -2102,18 +2102,18 @@
 #CHECK: error: invalid operand
 #CHECK: risbg	%r0,%r0,0,-1,0
 #CHECK: error: invalid operand
-#CHECK: risbg	%r0,%r0,0,64,0
+#CHECK: risbg	%r0,%r0,0,256,0
 #CHECK: error: invalid operand
 #CHECK: risbg	%r0,%r0,-1,0,0
 #CHECK: error: invalid operand
-#CHECK: risbg	%r0,%r0,64,0,0
+#CHECK: risbg	%r0,%r0,256,0,0
 
 	risbg	%r0,%r0,0,0,-1
 	risbg	%r0,%r0,0,0,64
 	risbg	%r0,%r0,0,-1,0
-	risbg	%r0,%r0,0,64,0
+	risbg	%r0,%r0,0,256,0
 	risbg	%r0,%r0,-1,0,0
-	risbg	%r0,%r0,64,0,0
+	risbg	%r0,%r0,256,0,0
 
 #CHECK: error: invalid operand
 #CHECK: rll	%r0,%r0,-524289

Modified: llvm/trunk/test/MC/SystemZ/insn-good.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good.s?rev=186070&r1=186069&r2=186070&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good.s Thu Jul 11 03:37:13 2013
@@ -5835,16 +5835,16 @@
 
 #CHECK: risbg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x55]
 #CHECK: risbg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55]
-#CHECK: risbg	%r0, %r0, 0, 63, 0      # encoding: [0xec,0x00,0x00,0x3f,0x00,0x55]
-#CHECK: risbg	%r0, %r0, 63, 0, 0      # encoding: [0xec,0x00,0x3f,0x00,0x00,0x55]
+#CHECK: risbg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
+#CHECK: risbg	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x55]
 #CHECK: risbg	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55]
 #CHECK: risbg	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x55]
 #CHECK: risbg	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x55]
 
 	risbg	%r0,%r0,0,0,0
 	risbg	%r0,%r0,0,0,63
-	risbg	%r0,%r0,0,63,0
-	risbg	%r0,%r0,63,0,0
+	risbg	%r0,%r0,0,255,0
+	risbg	%r0,%r0,255,0,0
 	risbg	%r0,%r15,0,0,0
 	risbg	%r15,%r0,0,0,0
 	risbg	%r4,%r5,6,7,8