[llvm] r185994 - Explicitly define ARMISelLowering::isFMAFasterThanFMulAndFAdd. No functionality change.

[Jim Grosbach]

Most excellent. Thanks!


On Jul 9, 2013, at 6:54 PM, Stephen Lin <stephenwlin at gmail.com> wrote:

> Author: stephenwlin
> Date: Tue Jul  9 20:54:24 2013
> New Revision: 185994
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=185994&view=rev
> Log:
> Explicitly define ARMISelLowering::isFMAFasterThanFMulAndFAdd. No functionality change.
> 
> Currently ARM is the only backend that supports FMA instructions (for at least some subtargets) but does not implement this virtual, so FMAs are never generated except from explicit fma intrinsic calls. Apparently this is due to the fact that it supports both fused (one rounding step) and unfused (two rounding step) multiply + add instructions. This patch clarifies that this the case without changing behavior by implementing the virtual function to simply return false, as the default TargetLoweringBase version does.
> 
> It is possible that some cpus perform the fused version faster than the unfused version and vice-versa, so the function implementation should be revisited if hard data is found.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=185994&r1=185993&r2=185994&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Jul  9 20:54:24 2013
> @@ -458,6 +458,17 @@ namespace llvm {
>     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
>                               const ARMSubtarget *ST) const;
> 
> +    /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
> +    /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
> +    /// expanded to FMAs when this method returns true, otherwise fmuladd is
> +    /// expanded to fmul + fadd.
> +    ///
> +    /// ARM supports both fused and unfused multiply-add operations; we already
> +    /// lower a pair of fmul and fmadd to the latter so it's not clear that there
> +    /// would be a gain or that the gain would be worthwhile enough to risk
> +    /// correctness bugs.
> +    virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const { return false; }
> +
>     SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
> 
>     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
> 
> 
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