[PATCH ] adding AVX 256bit register support to ghc_x86-64 calling convention (hopefully for both 3.4 and 3.3 point release)

[Carter Tazio Schonwald]

Hey All,

currently the GHC calling convention doesnt have support for using the AVX 256bit width registers. Attached is a patch that augments the GHC x86-64 calling convention with that support when vector types of that size are used. 

This change has been Ok'd by the GHC HQ devs responsible for the SIMD support recently added to ghc (as well as the principal author of the llvm backend for ghc ).  see the ghc ticket here http://hackage.haskell.org/trac/ghc/ticket/8033 for their indications of approval 

it'd be really great to have this patch in both the 3.4 and the pending 3.3 point release, because then the next GHC release could get some additional work to support AVX2   now rather than later. (in addition to the current support for 128bit simd) 

i've included the patch and an additional test case in the diff attached below

thanks!
-Carter
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