[llvm] r185855 - PPC: Mark vector CC action for SETO and SETONE as Expand

[Hal Finkel]

Author: hfinkel
Date: Mon Jul  8 15:00:03 2013
New Revision: 185855

URL: http://llvm.org/viewvc/llvm-project?rev=185855&view=rev
Log:
PPC: Mark vector CC action for SETO and SETONE as Expand

Another bug found by llvm-stress! This fixes hitting
  llvm_unreachable("Invalid integer vector compare condition");
at the end of getVCmpInst in PPCISelDAGToDAG.

Added:
    llvm/trunk/test/CodeGen/PowerPC/altivec-ord.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=185855&r1=185854&r2=185855&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jul  8 15:00:03 2013
@@ -487,6 +487,9 @@ PPCTargetLowering::PPCTargetLowering(PPC
     setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
     setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
     setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
+
+    setCondCodeAction(ISD::SETO,   MVT::v4f32, Expand);
+    setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
   }
 
   if (Subtarget->has64BitSupport()) {

Added: llvm/trunk/test/CodeGen/PowerPC/altivec-ord.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/altivec-ord.ll?rev=185855&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/altivec-ord.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/altivec-ord.ll Mon Jul  8 15:00:03 2013
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define <4 x i16> @test(<4 x float> %f, <4 x float> %g) {
+entry:
+	%r = fcmp ord <4 x float> %f, %g
+	%s = sext <4 x i1> %r to <4 x i16>
+	ret <4 x i16> %s
+}
+
+define <4 x i16> @test2(<4 x float> %f, <4 x float> %g) {
+entry:
+	%r = fcmp one <4 x float> %f, %g
+	%s = sext <4 x i1> %r to <4 x i16>
+	ret <4 x i16> %s
+}
+