[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

Weiming Zhao weimingz at codeaurora.org
Thu Jun 27 23:58:46 PDT 2013

Hi Tim,

Initially, we try to use GPRPair for 64-bit operands of inlineasm for ARM
However, it looks we still need to pack 64-data into GPRPair to support
syntax like "ldrexd $0, ${0:H}, [r0]" ( although "ldrexd $0, $1, [r0]" is
more appropriate for Thumb).

So I reverted my previous changes to the spill tests and added thumb tests
to inlineasm-64bit test.

I also added test cases for Q and R, tied operand and addressed the typo and


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-----Original Message-----
From: Tim Northover [mailto:t.p.northover at gmail.com] 
Sent: Tuesday, June 25, 2013 6:37 AM
To: Weiming Zhao
Cc: Renato Golin; Måns Rullgård; LLVM Commits
Subject: Re: [LLVMdev] Problems with 64-bit register operands of inline asm
on ARM

Hi Weiming,

> Tim, could you help to review it?

Of course.

I think this breaks thumb register pairs. When I compile your added tests
with a thumbv7 triple the output is clearly nonsense ("ldrd r0, , [r0]").
It's still valid syntax though, isn't it?

In fact, it looks like your test doesn't make use of the 'R and 'Q'
modifiers you're actually changing at all.

Also, am I misinterpreting or is there no test for the tied operand changes?
If so, there should be. In fact, it might be better as a separate commit

Some minor nits too:

> // If it's a use that is tied with a previouse def, it has no

Should be "previous".

> unsigned RegNum

Could we rename this to NumRegs? RegNum suggests it's an index rather than a
count to me and I nearly had a fit when I saw "RegNum != 2"
because of that (it's fine, of course).


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