R600: Initial support for vliw5 scheduling

[Vincent Lejeune]

Hi,

These 2 patches allows trans only instructions to be grouped with vector instructions to form 5 instructions bundle on vliw5 processors.
I had to remove the isTransOnly attribute of FLT_TO_INT_eg instructions because it looks like the docs are wrong saying it's a trans only instruction :
Single FLT_TO_INT_eg instructions does not write to PS register (trans only instructions always write to PS register) and there is no regression introduced when
making it non trans only. (SB backend seems to mark it not trans only, too )

I have another set of patches to generalize vliw 5 support to all non vector-only instructions but it's still WIP at the moment.


Vincent
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