[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Renato Golin]

Hi Weiming,

Do you have a way of running it against the kernel? Would be great to check
against it, too.

If not, I think Vinicius (cc'd) can lend us a hand. ;-)

Cheers,
Renato
On 24 Jun 2013 21:29, "Weiming Zhao" <weimingz at codeaurora.org> wrote:

> + Tim****
>
> ** **
>
> After I rebased the patch, I found 2 unit test fails:****
>
> test/CodeGen/ARM/gpr-paired-spill.ll****
>
> test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll****
>
> ** **
>
> This is because now we don’t require paired GPR for thumb mode
> ldrexd/strexd. ****
>
> So I updated unit test.  Tim, could you help to review it?****
>
> ** **
>
> Thanks,****
>
> Weiming****
>
> ** **
>
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation****
>
> ** **
>
> *From:* Renato Golin [mailto:renato.golin at linaro.org]
> *Sent:* Saturday, June 22, 2013 12:57 PM
> *To:* Zhao
> *Cc:* Jakob Stoklund Olesen; Måns Rullgård; Jim Grosbach; Kristof Beyls;
> Eric Christopher; LLVM Commits
> *Subject:* Re: [LLVMdev] Problems with 64-bit register operands of inline
> asm on ARM****
>
> ** **
>
> On 22 June 2013 18:58, <weimingz at codeaurora.org> wrote:****
>
> My patch can make integrated-as's job easier because it guarantees that an
> even reg is emitted for %0 place holder and the consecutive odd reg is
> available to be used.****
>
> ** **
>
> Looks good to me. We can worry about %0 later.****
>
> ** **
>
> cheers,****
>
> --renato****
>
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