[llvm] r184767 - [PowerPC] Support some miscellaneous mnemonics in the asm parser

[Ulrich Weigand]

Author: uweigand
Date: Mon Jun 24 13:08:03 2013
New Revision: 184767

URL: http://llvm.org/viewvc/llvm-project?rev=184767&view=rev
Log:

[PowerPC] Support some miscellaneous mnemonics in the asm parser

This adds support for the following extended mnemonics:
  xnop
  mr.
  not
  not.
  la


Modified:
    llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
    llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s

Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=184767&r1=184766&r2=184767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Mon Jun 24 13:08:03 2013
@@ -423,6 +423,15 @@ void PPCAsmParser::
 ProcessInstruction(MCInst &Inst,
                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   switch (Inst.getOpcode()) {
+  case PPC::LAx: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(PPC::LA);
+    TmpInst.addOperand(Inst.getOperand(0));
+    TmpInst.addOperand(Inst.getOperand(2));
+    TmpInst.addOperand(Inst.getOperand(1));
+    Inst = TmpInst;
+    break;
+  }
   case PPC::SLWI: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=184767&r1=184766&r2=184767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Jun 24 13:08:03 2013
@@ -2266,7 +2266,15 @@ class PPCAsmPseudo<string asm, dag iops>
 
 def : InstAlias<"sc", (SC 0)>;
 
+def : InstAlias<"xnop", (XORI R0, R0, 0)>;
+
 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
+def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
+
+def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
+def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
+
+def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
 
 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;

Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s?rev=184767&r1=184766&r2=184767&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s Mon Jun 24 13:08:03 2013
@@ -1899,15 +1899,20 @@
 
 # CHECK: nop                             # encoding: [0x60,0x00,0x00,0x00]
          nop
-# FIXME: xnop
+# CHECK: xori 0, 0, 0                    # encoding: [0x68,0x00,0x00,0x00]
+         xnop
 # CHECK: li 2, 128                       # encoding: [0x38,0x40,0x00,0x80]
          li 2, 128
 # CHECK: lis 2, 128                      # encoding: [0x3c,0x40,0x00,0x80]
          lis 2, 128
-# FIXME: la 2, 128(4)
+# CHECK: la 2, 128(4)
+         la 2, 128(4)
 # CHECK: mr 2, 3                         # encoding: [0x7c,0x62,0x1b,0x78]
          mr 2, 3
-# FIXME: mr. 2, 3
-# FIXME: not 2, 3
-# FIXME: not. 2, 3
+# CHECK: or. 2, 3, 3                     # encoding: [0x7c,0x62,0x1b,0x79]
+         mr. 2, 3
+# CHECK: nor 2, 3, 3                     # encoding: [0x7c,0x62,0x18,0xf8]
+         not 2, 3
+# CHECK: nor. 2, 3, 3                    # encoding: [0x7c,0x62,0x18,0xf9]
+         not. 2, 3