[llvm] r184707 - ARM: check predicate bits for thumb instructions

[Amaury de la Vieuville]

Author: amaury.dlv
Date: Mon Jun 24 04:15:01 2013
New Revision: 184707

URL: http://llvm.org/viewvc/llvm-project?rev=184707&view=rev
Log:
ARM: check predicate bits for thumb instructions

When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=184707&r1=184706&r2=184707&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Jun 24 04:15:01 2013
@@ -754,21 +754,25 @@ DecodeStatus ThumbDisassembler::getInstr
     return result;
   }
 
-  MI.clear();
-  result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
-  if (result != MCDisassembler::Fail) {
-    Size = 4;
-    UpdateThumbVFPPredicate(MI);
-    return result;
+  if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
+    MI.clear();
+    result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
+    if (result != MCDisassembler::Fail) {
+      Size = 4;
+      UpdateThumbVFPPredicate(MI);
+      return result;
+    }
   }
 
-  MI.clear();
-  result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
-                             this, STI);
-  if (result != MCDisassembler::Fail) {
-    Size = 4;
-    Check(result, AddThumbPredicate(MI));
-    return result;
+  if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
+    MI.clear();
+    result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
+                               this, STI);
+    if (result != MCDisassembler::Fail) {
+      Size = 4;
+      Check(result, AddThumbPredicate(MI));
+      return result;
+    }
   }
 
   if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt?rev=184707&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt Mon Jun 24 04:15:01 2013
@@ -0,0 +1,9 @@
+# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
+
+# VMOV
+# RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VDUP
+# RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt?rev=184707&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt Mon Jun 24 04:15:01 2013
@@ -0,0 +1,9 @@
+# VFP instructions with invalid predicate bits (pred != 0b1110)
+
+# VABS
+# RUN: echo "0x40 0xde 0x00 0x0a" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VMLA
+# RUN: echo "0xf0 0xde 0xe0 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding