[llvm] r183993 - SelectionDAG: Fix incorrect condition checks in some cases of folding FADD/FMUL combinations; also improve accuracy of comments
Stephen Lin
stephenwlin at gmail.com
Fri Jun 14 11:17:35 PDT 2013
Author: stephenwlin
Date: Fri Jun 14 13:17:35 2013
New Revision: 183993
URL: http://llvm.org/viewvc/llvm-project?rev=183993&view=rev
Log:
SelectionDAG: Fix incorrect condition checks in some cases of folding FADD/FMUL combinations; also improve accuracy of comments
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/fp-fast.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=183993&r1=183992&r2=183993&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jun 14 13:17:35 2013
@@ -5919,7 +5919,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N
ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
- // (fadd (fmul c, x), x) -> (fmul c+1, x)
+ // (fadd (fmul c, x), x) -> (fmul x, c+1)
if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
SDValue(CFP00, 0),
@@ -5928,7 +5928,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N
N1, NewCFP);
}
- // (fadd (fmul x, c), x) -> (fmul c+1, x)
+ // (fadd (fmul x, c), x) -> (fmul x, c+1)
if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
SDValue(CFP01, 0),
@@ -5937,7 +5937,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N
N1, NewCFP);
}
- // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x)
+ // (fadd (fmul c, x), (fadd x, x)) -> (fmul x, c+2)
if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
N1.getOperand(0) == N1.getOperand(1) &&
N0.getOperand(1) == N1.getOperand(0)) {
@@ -5948,7 +5948,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N
N0.getOperand(1), NewCFP);
}
- // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x)
+ // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
N1.getOperand(0) == N1.getOperand(1) &&
N0.getOperand(0) == N1.getOperand(0)) {
@@ -5964,7 +5964,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N
ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
- // (fadd x, (fmul c, x)) -> (fmul c+1, x)
+ // (fadd x, (fmul c, x)) -> (fmul x, c+1)
if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
SDValue(CFP10, 0),
@@ -5973,7 +5973,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N
N0, NewCFP);
}
- // (fadd x, (fmul x, c)) -> (fmul c+1, x)
+ // (fadd x, (fmul x, c)) -> (fmul x, c+1)
if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
SDValue(CFP11, 0),
@@ -5983,26 +5983,26 @@ SDValue DAGCombiner::visitFADD(SDNode *N
}
- // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x)
- if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD &&
- N1.getOperand(0) == N1.getOperand(1) &&
- N0.getOperand(1) == N1.getOperand(0)) {
+ // (fadd (fadd x, x), (fmul c, x)) -> (fmul x, c+2)
+ if (CFP10 && !CFP11 && N0.getOpcode() == ISD::FADD &&
+ N0.getOperand(0) == N0.getOperand(1) &&
+ N1.getOperand(1) == N0.getOperand(0)) {
SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
SDValue(CFP10, 0),
DAG.getConstantFP(2.0, VT));
return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
- N0.getOperand(1), NewCFP);
+ N1.getOperand(1), NewCFP);
}
- // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x)
- if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD &&
- N1.getOperand(0) == N1.getOperand(1) &&
- N0.getOperand(0) == N1.getOperand(0)) {
+ // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
+ if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
+ N0.getOperand(0) == N0.getOperand(1) &&
+ N1.getOperand(0) == N0.getOperand(0)) {
SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
SDValue(CFP11, 0),
DAG.getConstantFP(2.0, VT));
return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
- N0.getOperand(0), NewCFP);
+ N1.getOperand(0), NewCFP);
}
}
Modified: llvm/trunk/test/CodeGen/X86/fp-fast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-fast.ll?rev=183993&r1=183992&r2=183993&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fp-fast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fp-fast.ll Fri Jun 14 13:17:35 2013
@@ -26,6 +26,42 @@ define float @test2(float %a) {
; CHECK: test3
define float @test3(float %a) {
; CHECK-NOT: addss
+; CHECK: mulss
+; CHECK-NOT: addss
+; CHECK: ret
+ %t1 = fmul float %a, 4.0
+ %t2 = fadd float %a, %a
+ %r = fadd float %t1, %t2
+ ret float %r
+}
+
+; CHECK: test4
+define float @test4(float %a) {
+; CHECK-NOT: addss
+; CHECK: mulss
+; CHECK-NOT: addss
+; CHECK: ret
+ %t1 = fadd float %a, %a
+ %t2 = fmul float 4.0, %a
+ %r = fadd float %t1, %t2
+ ret float %r
+}
+
+; CHECK: test5
+define float @test5(float %a) {
+; CHECK-NOT: addss
+; CHECK: mulss
+; CHECK-NOT: addss
+; CHECK: ret
+ %t1 = fadd float %a, %a
+ %t2 = fmul float %a, 4.0
+ %r = fadd float %t1, %t2
+ ret float %r
+}
+
+; CHECK: test6
+define float @test6(float %a) {
+; CHECK-NOT: addss
; CHECK: xorps
; CHECK-NOT: addss
; CHECK: ret
@@ -35,8 +71,20 @@ define float @test3(float %a) {
ret float %r
}
-; CHECK: test4
-define float @test4(float %a) {
+; CHECK: test7
+define float @test7(float %a) {
+; CHECK-NOT: addss
+; CHECK: xorps
+; CHECK-NOT: addss
+; CHECK: ret
+ %t1 = fmul float %a, 2.0
+ %t2 = fadd float %a, %a
+ %r = fsub float %t1, %t2
+ ret float %r
+}
+
+; CHECK: test8
+define float @test8(float %a) {
; CHECK-NOT: fma
; CHECK-NOT: mul
; CHECK-NOT: add
@@ -46,8 +94,29 @@ define float @test4(float %a) {
ret float %t2
}
-; CHECK: test5
-define float @test5(float %a) {
+; CHECK: test9
+define float @test9(float %a) {
+; CHECK-NOT: fma
+; CHECK-NOT: mul
+; CHECK-NOT: add
+; CHECK: ret
+ %t1 = fmul float 0.0, %a
+ %t2 = fadd float %t1, %a
+ ret float %t2
+}
+
+; CHECK: test10
+define float @test10(float %a) {
+; CHECK-NOT: add
+; CHECK: vxorps
+; CHECK: ret
+ %t1 = fsub float -0.0, %a
+ %t2 = fadd float %a, %t1
+ ret float %t2
+}
+
+; CHECK: test11
+define float @test11(float %a) {
; CHECK-NOT: add
; CHECK: vxorps
; CHECK: ret
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