[llvm] r183975 - ARM: fix thumb coprocessor instruction with pre-writeback disassembly

[Amaury de la Vieuville]

Author: amaury.dlv
Date: Fri Jun 14 06:21:35 2013
New Revision: 183975

URL: http://llvm.org/viewvc/llvm-project?rev=183975&view=rev
Log:
ARM: fix thumb coprocessor instruction with pre-writeback disassembly

was        stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=183975&r1=183974&r2=183975&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Jun 14 06:21:35 2013
@@ -3632,7 +3632,7 @@ multiclass t2LdStCop<bits<4> op31_28, bi
     let DecoderMethod = "DecodeCopMemInstruction";
   }
   def _PRE : T2CI<op31_28,
-                  (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
+                  (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
                   asm, "\t$cop, $CRd, $addr!"> {
     bits<13> addr;
     bits<4> cop;

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=183975&r1=183974&r2=183975&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Fri Jun 14 06:21:35 2013
@@ -221,6 +221,9 @@
 # CHECK:	stc2	p12, c15, [r9], {137}
 0x89 0xfc 0x89 0xfc
 
+# CHECK:	stc2	p0, c0, [r0, #0]!
+0xa0 0xfd 0x00 0x00
+
 # CHECK:	vmov	r1, r0, d11
 0x50 0xec 0x1b 0x1b