[llvm] r183731 - ARM: Enforce decoding rules for VLDn instructions
Amaury de la Vieuville
amaury.dlv at gmail.com
Tue Jun 11 01:14:14 PDT 2013
Author: amaury.dlv
Date: Tue Jun 11 03:14:14 2013
New Revision: 183731
URL: http://llvm.org/viewvc/llvm-project?rev=183731&view=rev
Log:
ARM: Enforce decoding rules for VLDn instructions
Added:
llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt
Removed:
llvm/trunk/test/MC/Disassembler/ARM/invalid-VST-arm.txt
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=183731&r1=183730&r2=183731&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Jun 11 03:14:14 2013
@@ -626,7 +626,7 @@ class VLD1D<bits<4> op7_4, string Dt>
"vld1", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
}
class VLD1Q<bits<4> op7_4, string Dt>
: NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
@@ -634,7 +634,7 @@ class VLD1Q<bits<4> op7_4, string Dt>
"vld1", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
}
def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
@@ -655,7 +655,7 @@ multiclass VLD1DWB<bits<4> op7_4, string
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
}
def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
@@ -663,7 +663,7 @@ multiclass VLD1DWB<bits<4> op7_4, string
"vld1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
}
}
@@ -674,7 +674,7 @@ multiclass VLD1QWB<bits<4> op7_4, string
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
}
def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
@@ -682,7 +682,7 @@ multiclass VLD1QWB<bits<4> op7_4, string
"vld1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
}
}
@@ -703,7 +703,7 @@ class VLD1D3<bits<4> op7_4, string Dt>
"$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
}
multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
@@ -712,7 +712,7 @@ multiclass VLD1D3WB<bits<4> op7_4, strin
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
}
def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
@@ -720,7 +720,7 @@ multiclass VLD1D3WB<bits<4> op7_4, strin
"vld1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
}
}
@@ -744,7 +744,7 @@ class VLD1D4<bits<4> op7_4, string Dt>
"$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
}
multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
@@ -753,7 +753,7 @@ multiclass VLD1D4WB<bits<4> op7_4, strin
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
}
def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
@@ -761,7 +761,7 @@ multiclass VLD1D4WB<bits<4> op7_4, strin
"vld1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
}
}
@@ -786,7 +786,7 @@ class VLD2<bits<4> op11_8, bits<4> op7_4
"vld2", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST2Instruction";
}
def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
@@ -810,7 +810,7 @@ multiclass VLD2WB<bits<4> op11_8, bits<4
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
}
def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
@@ -818,7 +818,7 @@ multiclass VLD2WB<bits<4> op11_8, bits<4
"vld2", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
}
}
@@ -853,7 +853,7 @@ class VLD3D<bits<4> op11_8, bits<4> op7_
"vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
let Rm = 0b1111;
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST3Instruction";
}
def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
@@ -872,7 +872,7 @@ class VLD3DWB<bits<4> op11_8, bits<4> op
"vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST3Instruction";
}
def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
@@ -912,7 +912,7 @@ class VLD4D<bits<4> op11_8, bits<4> op7_
"vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST4Instruction";
}
def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
@@ -931,7 +931,7 @@ class VLD4DWB<bits<4> op11_8, bits<4> op
"vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVLDInstruction";
+ let DecoderMethod = "DecodeVLDST4Instruction";
}
def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
@@ -1580,14 +1580,14 @@ class VST1D<bits<4> op7_4, string Dt>
IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
}
class VST1Q<bits<4> op7_4, string Dt>
: NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
}
def VST1d8 : VST1D<{0,0,0,?}, "8">;
@@ -1608,7 +1608,7 @@ multiclass VST1DWB<bits<4> op7_4, string
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
}
def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
@@ -1617,7 +1617,7 @@ multiclass VST1DWB<bits<4> op7_4, string
"vst1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
}
}
@@ -1628,7 +1628,7 @@ multiclass VST1QWB<bits<4> op7_4, string
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
}
def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
@@ -1637,7 +1637,7 @@ multiclass VST1QWB<bits<4> op7_4, string
"vst1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
}
}
@@ -1659,7 +1659,7 @@ class VST1D3<bits<4> op7_4, string Dt>
IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
}
multiclass VST1D3WB<bits<4> op7_4, string Dt> {
def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
@@ -1668,7 +1668,7 @@ multiclass VST1D3WB<bits<4> op7_4, strin
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
}
def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
@@ -1677,7 +1677,7 @@ multiclass VST1D3WB<bits<4> op7_4, strin
"vst1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
}
}
@@ -1704,7 +1704,7 @@ class VST1D4<bits<4> op7_4, string Dt>
[]> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
}
multiclass VST1D4WB<bits<4> op7_4, string Dt> {
def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
@@ -1713,7 +1713,7 @@ multiclass VST1D4WB<bits<4> op7_4, strin
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
}
def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
@@ -1722,7 +1722,7 @@ multiclass VST1D4WB<bits<4> op7_4, strin
"vst1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST1Instruction";
+ let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
}
}
@@ -1748,7 +1748,7 @@ class VST2<bits<4> op11_8, bits<4> op7_4
itin, "vst2", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST2Instruction";
+ let DecoderMethod = "DecodeVLDST2Instruction";
}
def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
@@ -1772,7 +1772,7 @@ multiclass VST2DWB<bits<4> op11_8, bits<
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST2Instruction";
+ let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
}
def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
@@ -1780,7 +1780,7 @@ multiclass VST2DWB<bits<4> op11_8, bits<
"vst2", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST2Instruction";
+ let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
}
}
@@ -1791,7 +1791,7 @@ multiclass VST2QWB<bits<4> op7_4, string
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST2Instruction";
+ let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
}
def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
@@ -1800,7 +1800,7 @@ multiclass VST2QWB<bits<4> op7_4, string
"vst2", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST2Instruction";
+ let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
}
}
@@ -1835,7 +1835,7 @@ class VST3D<bits<4> op11_8, bits<4> op7_
"vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
let Rm = 0b1111;
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVST3Instruction";
+ let DecoderMethod = "DecodeVLDST3Instruction";
}
def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
@@ -1854,7 +1854,7 @@ class VST3DWB<bits<4> op11_8, bits<4> op
"vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{4} = Rn{4};
- let DecoderMethod = "DecodeVST3Instruction";
+ let DecoderMethod = "DecodeVLDST3Instruction";
}
def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
@@ -1894,7 +1894,7 @@ class VST4D<bits<4> op11_8, bits<4> op7_
"", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST4Instruction";
+ let DecoderMethod = "DecodeVLDST4Instruction";
}
def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
@@ -1913,7 +1913,7 @@ class VST4DWB<bits<4> op11_8, bits<4> op
"vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
- let DecoderMethod = "DecodeVST4Instruction";
+ let DecoderMethod = "DecodeVLDST4Instruction";
}
def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=183731&r1=183730&r2=183731&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Jun 11 03:14:14 2013
@@ -241,15 +241,15 @@ static DecodeStatus DecodeBranchImmInstr
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
@@ -2430,47 +2430,55 @@ static DecodeStatus DecodeVLDInstruction
return S;
}
-static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn,
- uint64_t Addr, const void* Decoder) {
+static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
unsigned type = fieldFromInstruction(Insn, 8, 4);
unsigned align = fieldFromInstruction(Insn, 4, 2);
- if(type == 7 && (align & 2)) return MCDisassembler::Fail;
- if(type == 10 && align == 3) return MCDisassembler::Fail;
- if(type == 6 && (align & 2)) return MCDisassembler::Fail;
-
- return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
+ if (type == 6 && (align & 2)) return MCDisassembler::Fail;
+ if (type == 7 && (align & 2)) return MCDisassembler::Fail;
+ if (type == 10 && align == 3) return MCDisassembler::Fail;
+
+ unsigned load = fieldFromInstruction(Insn, 21, 1);
+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
}
-static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn,
- uint64_t Addr, const void* Decoder) {
+static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
unsigned size = fieldFromInstruction(Insn, 6, 2);
- if(size == 3) return MCDisassembler::Fail;
+ if (size == 3) return MCDisassembler::Fail;
unsigned type = fieldFromInstruction(Insn, 8, 4);
unsigned align = fieldFromInstruction(Insn, 4, 2);
- if(type == 8 && align == 3) return MCDisassembler::Fail;
- if(type == 9 && align == 3) return MCDisassembler::Fail;
-
- return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
+ if (type == 8 && align == 3) return MCDisassembler::Fail;
+ if (type == 9 && align == 3) return MCDisassembler::Fail;
+
+ unsigned load = fieldFromInstruction(Insn, 21, 1);
+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
}
-static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn,
- uint64_t Addr, const void* Decoder) {
+static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
unsigned size = fieldFromInstruction(Insn, 6, 2);
- if(size == 3) return MCDisassembler::Fail;
+ if (size == 3) return MCDisassembler::Fail;
unsigned align = fieldFromInstruction(Insn, 4, 2);
- if(align & 2) return MCDisassembler::Fail;
+ if (align & 2) return MCDisassembler::Fail;
- return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
+ unsigned load = fieldFromInstruction(Insn, 21, 1);
+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
}
-static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn,
- uint64_t Addr, const void* Decoder) {
+static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
unsigned size = fieldFromInstruction(Insn, 6, 2);
- if(size == 3) return MCDisassembler::Fail;
+ if (size == 3) return MCDisassembler::Fail;
- return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
+ unsigned load = fieldFromInstruction(Insn, 21, 1);
+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
}
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt?rev=183731&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt Tue Jun 11 03:14:14 2013
@@ -0,0 +1,62 @@
+# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
+# RUN: echo "0xaf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
+# RUN: echo "0xbf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
+# RUN: echo "0xbf 0x8a 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
+# RUN: echo "0xaf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
+# RUN: echo "0xbf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
+# RUN: echo "0x4f 0xa8 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
+# RUN: echo "0x4f 0xa9 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST3 multi-element, size = 0b11 -> undefined
+# RUN: echo "0xbf 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST3 multi-element, align = 0b10 -> undefined
+# RUN: echo "0x6f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST3 multi-element, align = 0b11 -> undefined
+# RUN: echo "0x7f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VST4 multi-element, size = 0b11 -> undefined
+# RUN: echo "0xcf 0x50 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VLD1 multi-element, type=0b1010 align=0b11
+# RUN: echo "0x24 0xf9 0xbf 0x8a" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VLD1 multi-element type=0b0111 align=0b1x
+# RUN: echo "0x24 0xf9 0xbf 0x87" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VLD1 multi-element type=0b0010 align=0b1x
+# RUN: echo "0x24 0xf9 0xbf 0x86" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VLD2 multi-element size=0b11
+# RUN: echo "0x60 0xf9 0xcf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VLD2 multi-element type=0b1111 align=0b11
+# RUN: echo "0x60 0xf9 0xbf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VLD2 multi-element type=0b1001 align=0b11
+# RUN: echo "0x60 0xf9 0xbf 0x09" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VLD3 multi-element size=0b11
+# RUN: echo "0x60 0xf9 0x7f 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VLD3 multi-element align=0b1x
+# RUN: echo "0x60 0xf9 0xcf 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VLD4 multi-element size=0b11
+# RUN: echo "0x60 0xf9 0xcd 0x11" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding
+
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-VST-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VST-arm.txt?rev=183730&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VST-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VST-arm.txt (removed)
@@ -1,35 +0,0 @@
-# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
-# RUN: echo "0xaf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
-# RUN: echo "0xbf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
-# RUN: echo "0xbf 0x8a 0x03 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
-# RUN: echo "0xaf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
-# RUN: echo "0xbf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
-# RUN: echo "0x4f 0xa8 0x07 0xf7" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
-# RUN: echo "0x4f 0xa9 0x07 0xf7" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST3 multi-element, size = 0b11 -> undefined
-# RUN: echo "0xbf 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST3 multi-element, align = 0b10 -> undefined
-# RUN: echo "0x6f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST3 multi-element, align = 0b11 -> undefined
-# RUN: echo "0x7f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# VST4 multi-element, size = 0b11 -> undefined
-# RUN: echo "0xcf 0x50 0x03 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
-
Modified: llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neont2.txt?rev=183731&r1=183730&r2=183731&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neont2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neont2.txt Tue Jun 11 03:14:14 2013
@@ -1629,9 +1629,6 @@
0xc0 0xf9 0x4f 0x1b
# CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
-0x63 0xf9 0x37 0xc9
-# CHECK: vld2.8 {d28, d30}, [r3:256], r7
-
# rdar://10798451
0xe7 0xf9 0x32 0x1d
# CHECK vld2.8 {d17[], d19[]}, [r7:16], r2
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