[llvm] r183624 - ARM FastISel fix load register classes

[Chandler Carruth]

On Sat, Jun 8, 2013 at 5:20 PM, JF Bastien <jfb at google.com> wrote:

> Author: jfb
> Date: Sat Jun  8 19:20:24 2013
> New Revision: 183624
>
> URL: http://llvm.org/viewvc/llvm-project?rev=183624&view=rev
> Log:
> ARM FastISel fix load register classes
>
> The register classes when emitting loads weren't quite restricting enough,
> leading to MI verification failure on the result register.
>
> These are new failures that weren't there the first time I tried enabling
> ARM FastISel for new targets.
>

Is this something you can add a regression test that specifically exercises
the issue so we don't regress? (I realize that you can likely reproduce
this just be enabling various verifiers on existing tests, or enabling fast
isel on them, but it'd be good to explicitly test the things you end up
fixing.


>
> Modified:
>     llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=183624&r1=183623&r2=183624&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Sat Jun  8 19:20:24 2013
> @@ -1026,7 +1026,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, un
>            useAM3 = true;
>          }
>        }
> -      RC = &ARM::GPRRegClass;
> +      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
>        break;
>      case MVT::i16:
>        if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
> @@ -1041,7 +1041,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, un
>          Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
>          useAM3 = true;
>        }
> -      RC = &ARM::GPRRegClass;
> +      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
>        break;
>      case MVT::i32:
>        if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
> @@ -1055,7 +1055,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, un
>        } else {
>          Opc = ARM::LDRi12;
>        }
> -      RC = &ARM::GPRRegClass;
> +      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
>        break;
>      case MVT::f32:
>        if (!Subtarget->hasVFP2()) return false;
> @@ -1064,7 +1064,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, un
>          needVMOV = true;
>          VT = MVT::i32;
>          Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
> -        RC = &ARM::GPRRegClass;
> +        RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
>        } else {
>          Opc = ARM::VLDRS;
>          RC = TLI.getRegClassFor(VT);
>
>
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