[llvm] r183612 - ARM: fix VMOVvnf32 decoding when ambiguous with VCVT

[Amaury de la Vieuville]

Author: amaury.dlv
Date: Sat Jun  8 08:54:05 2013
New Revision: 183612

URL: http://llvm.org/viewvc/llvm-project?rev=183612&view=rev
Log:
ARM: fix VMOVvnf32 decoding when ambiguous with VCVT

Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=183612&r1=183611&r2=183612&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Sat Jun  8 08:54:05 2013
@@ -4470,11 +4470,13 @@ static DecodeStatus DecodeVCVTD(MCInst &
   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
   unsigned imm = fieldFromInstruction(Insn, 16, 6);
   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
+  unsigned op = fieldFromInstruction(Insn, 5, 1);
 
   DecodeStatus S = MCDisassembler::Success;
 
   // VMOVv2f32 is ambiguous with these decodings.
   if (!(imm & 0x38) && cmode == 0xF) {
+    if (op == 1) return MCDisassembler::Fail;
     Inst.setOpcode(ARM::VMOVv2f32);
     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
   }
@@ -4498,11 +4500,13 @@ static DecodeStatus DecodeVCVTQ(MCInst &
   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
   unsigned imm = fieldFromInstruction(Insn, 16, 6);
   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
+  unsigned op = fieldFromInstruction(Insn, 5, 1);
 
   DecodeStatus S = MCDisassembler::Success;
 
   // VMOVv4f32 is ambiguous with these decodings.
   if (!(imm & 0x38) && cmode == 0xF) {
+    if (op == 1) return MCDisassembler::Fail;
     Inst.setOpcode(ARM::VMOVv4f32);
     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
   }

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt?rev=183612&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt Sat Jun  8 08:54:05 2013
@@ -0,0 +1,7 @@
+# VMOV cmode=0b1111 op=1
+# RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VMOV cmode=0b1111 op=1
+# RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding