[llvm] r183485 - Don't cache the instruction info and register info objects.
Bill Wendling
isanbard at gmail.com
Thu Jun 6 22:00:11 PDT 2013
Author: void
Date: Fri Jun 7 00:00:11 2013
New Revision: 183485
URL: http://llvm.org/viewvc/llvm-project?rev=183485&view=rev
Log:
Don't cache the instruction info and register info objects.
These objects are internal to the TargetMachine object and may change.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=183485&r1=183484&r2=183485&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Fri Jun 7 00:00:11 2013
@@ -33,7 +33,6 @@ namespace {
class AArch64DAGToDAGISel : public SelectionDAGISel {
AArch64TargetMachine &TM;
- const AArch64InstrInfo *TII;
/// Keep a pointer to the AArch64Subtarget around so that we can
/// make the right decision when generating code for different targets.
@@ -43,7 +42,6 @@ public:
explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
CodeGenOpt::Level OptLevel)
: SelectionDAGISel(tm, OptLevel), TM(tm),
- TII(static_cast<const AArch64InstrInfo*>(TM.getInstrInfo())),
Subtarget(&TM.getSubtarget<AArch64Subtarget>()) {
}
@@ -243,12 +241,12 @@ SDNode *AArch64DAGToDAGISel::TrySelectTo
SDValue
AArch64DAGToDAGISel::getConstantPoolItemAddress(SDLoc DL,
const Constant *CV) {
- EVT PtrVT = TLI->getPointerTy();
+ EVT PtrVT = getTargetLowering()->getPointerTy();
- switch (TLI->getTargetMachine().getCodeModel()) {
+ switch (getTargetLowering()->getTargetMachine().getCodeModel()) {
case CodeModel::Small: {
unsigned Alignment =
- TLI->getDataLayout()->getABITypeAlignment(CV->getType());
+ getTargetLowering()->getDataLayout()->getABITypeAlignment(CV->getType());
return CurDAG->getNode(
AArch64ISD::WrapperSmall, DL, PtrVT,
CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_NO_FLAG),
@@ -312,7 +310,8 @@ SDNode *AArch64DAGToDAGISel::SelectToLit
MemType.getSizeInBits()),
UnsignedVal);
SDValue PoolAddr = getConstantPoolItemAddress(DL, CV);
- unsigned Alignment = TLI->getDataLayout()->getABITypeAlignment(CV->getType());
+ unsigned Alignment =
+ getTargetLowering()->getDataLayout()->getABITypeAlignment(CV->getType());
return CurDAG->getExtLoad(Extension, DL, DestType, CurDAG->getEntryNode(),
PoolAddr,
@@ -327,7 +326,8 @@ SDNode *AArch64DAGToDAGISel::LowerToFPLi
const ConstantFP *FV = cast<ConstantFPSDNode>(Node)->getConstantFPValue();
EVT DestType = Node->getValueType(0);
- unsigned Alignment = TLI->getDataLayout()->getABITypeAlignment(FV->getType());
+ unsigned Alignment =
+ getTargetLowering()->getDataLayout()->getABITypeAlignment(FV->getType());
SDValue PoolAddr = getConstantPoolItemAddress(DL, FV);
return CurDAG->getLoad(DestType, DL, CurDAG->getEntryNode(), PoolAddr,
@@ -473,7 +473,7 @@ SDNode *AArch64DAGToDAGISel::Select(SDNo
AArch64::ATOMIC_CMP_SWAP_I64);
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(Node)->getIndex();
- EVT PtrTy = TLI->getPointerTy();
+ EVT PtrTy = getTargetLowering()->getPointerTy();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, PtrTy);
return CurDAG->SelectNodeTo(Node, AArch64::ADDxxi_lsl0_s, PtrTy,
TFI, CurDAG->getTargetConstant(0, PtrTy));
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=183485&r1=183484&r2=183485&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Jun 7 00:00:11 2013
@@ -39,12 +39,8 @@ static TargetLoweringObjectFile *createT
llvm_unreachable("unknown subtarget type");
}
-
AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
- : TargetLowering(TM, createTLOF(TM)),
- Subtarget(&TM.getSubtarget<AArch64Subtarget>()),
- RegInfo(TM.getRegisterInfo()),
- Itins(TM.getInstrItineraryData()) {
+ : TargetLowering(TM, createTLOF(TM)), Itins(TM.getInstrItineraryData()) {
// SIMD compares set the entire lane's bits to 1
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
@@ -1928,7 +1924,7 @@ AArch64TargetLowering::LowerGlobalAddres
}
unsigned char HiFixup, LoFixup;
- bool UseGOT = Subtarget->GVIsIndirectSymbol(GV, RelocM);
+ bool UseGOT = getSubtarget()->GVIsIndirectSymbol(GV, RelocM);
if (UseGOT) {
HiFixup = AArch64II::MO_GOT;
@@ -2024,7 +2020,7 @@ SDValue AArch64TargetLowering::LowerTLSD
SDValue
AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
SelectionDAG &DAG) const {
- assert(Subtarget->isTargetELF() &&
+ assert(getSubtarget()->isTargetELF() &&
"TLS not implemented for non-ELF targets");
assert(getTargetMachine().getCodeModel() == CodeModel::Small
&& "TLS only supported in small memory model");
@@ -2799,7 +2795,7 @@ AArch64TargetLowering::PerformDAGCombine
switch (N->getOpcode()) {
default: break;
case ISD::AND: return PerformANDCombine(N, DCI);
- case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
+ case ISD::OR: return PerformORCombine(N, DCI, getSubtarget());
case ISD::SRA: return PerformSRACombine(N, DCI);
}
return SDValue();
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=183485&r1=183484&r2=183485&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Fri Jun 7 00:00:11 2013
@@ -247,9 +247,11 @@ public:
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
private:
- const AArch64Subtarget *Subtarget;
- const TargetRegisterInfo *RegInfo;
const InstrItineraryData *Itins;
+
+ const AArch64Subtarget *getSubtarget() const {
+ return &getTargetMachine().getSubtarget<AArch64Subtarget>();
+ }
};
} // namespace llvm
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=183485&r1=183484&r2=183485&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Fri Jun 7 00:00:11 2013
@@ -36,7 +36,7 @@ using namespace llvm;
AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
: AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
- RI(*this, STI), Subtarget(STI) {}
+ Subtarget(STI) {}
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp?rev=183485&r1=183484&r2=183485&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp Fri Jun 7 00:00:11 2013
@@ -29,9 +29,8 @@
using namespace llvm;
-AArch64RegisterInfo::AArch64RegisterInfo(const AArch64InstrInfo &tii,
- const AArch64Subtarget &sti)
- : AArch64GenRegisterInfo(AArch64::X30), TII(tii) {
+AArch64RegisterInfo::AArch64RegisterInfo()
+ : AArch64GenRegisterInfo(AArch64::X30) {
}
const uint16_t *
@@ -122,6 +121,8 @@ AArch64RegisterInfo::eliminateFrameIndex
return;
}
+ const AArch64InstrInfo &TII =
+ *static_cast<const AArch64InstrInfo*>(MF.getTarget().getInstrInfo());
int MinOffset, MaxOffset, OffsetScale;
if (MI.getOpcode() == AArch64::ADDxxi_lsl0_s) {
MinOffset = 0;
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h?rev=183485&r1=183484&r2=183485&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h Fri Jun 7 00:00:11 2013
@@ -25,12 +25,7 @@ class AArch64InstrInfo;
class AArch64Subtarget;
struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
-private:
- const AArch64InstrInfo &TII;
-
-public:
- AArch64RegisterInfo(const AArch64InstrInfo &tii,
- const AArch64Subtarget &sti);
+ AArch64RegisterInfo();
const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const uint32_t *getCallPreservedMask(CallingConv::ID) const;
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