[llvm] r183132 - R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()

Tom Stellard tom at stellard.net
Mon Jun 3 11:22:45 PDT 2013


On Mon, Jun 03, 2013 at 02:02:53PM -0400, Rafael Ávila De Espíndola wrote:
> Test case ?
> 
Hi Rafael,

There are tests for these bugs in later commits mostly
work-item-intrinsics.ll

Most of these bugs were uncovered while working on a new feature for the
backend.  Usually when this happens I make commits like this:

r1 - Bug Fix #1
r2 - Bug Fix #2
r3 - New Feature + Bug tests

I don't like to push commits that have know bugs, even if the bug fix
is coming in the next commit.  The main reason for this is to make the
history more easily bisectable in case of other bugs.  Unfortunately,
this meas that tests are not included in the same commit as the fixes,
but I consider a cleaner history more important.

-Tom

> Sent from my iPhone
> 
> On 2013-06-03, at 13:39, Tom Stellard <thomas.stellard at amd.com> wrote:
> 
> > Author: tstellar
> > Date: Mon Jun  3 12:39:46 2013
> > New Revision: 183132
> > 
> > URL: http://llvm.org/viewvc/llvm-project?rev=183132&view=rev
> > Log:
> > R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()
> > 
> > The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
> > SGPR.  This kind of copy is not possible, so we need to detect
> > VGPR->SGPR copies and do something else.  The current strategy is to
> > replace these copies with VGPR->VGPR copies and hope that all the users
> > of CopyToReg can accept VGPRs as arguments.
> > 
> > Modified:
> >    llvm/trunk/lib/Target/R600/AMDILISelDAGToDAG.cpp
> > 
> > Modified: llvm/trunk/lib/Target/R600/AMDILISelDAGToDAG.cpp
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDILISelDAGToDAG.cpp?rev=183132&r1=183131&r2=183132&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/R600/AMDILISelDAGToDAG.cpp (original)
> > +++ llvm/trunk/lib/Target/R600/AMDILISelDAGToDAG.cpp Mon Jun  3 12:39:46 2013
> > @@ -18,6 +18,7 @@
> > #include "R600InstrInfo.h"
> > #include "SIISelLowering.h"
> > #include "llvm/ADT/ValueMap.h"
> > +#include "llvm/CodeGen/MachineRegisterInfo.h"
> > #include "llvm/CodeGen/PseudoSourceValue.h"
> > #include "llvm/CodeGen/SelectionDAG.h"
> > #include "llvm/CodeGen/SelectionDAGISel.h"
> > @@ -649,18 +650,45 @@ bool AMDGPUDAGToDAGISel::SelectADDRIndir
> > 
> > void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
> > 
> > +  if (Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX) {
> > +    return;
> > +  }
> > +
> >   // Go over all selected nodes and try to fold them a bit more
> >   const AMDGPUTargetLowering& Lowering = ((const AMDGPUTargetLowering&)TLI);
> >   for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
> >        E = CurDAG->allnodes_end(); I != E; ++I) {
> > 
> > -    MachineSDNode *Node = dyn_cast<MachineSDNode>(I);
> > -    if (!Node)
> > +    SDNode *Node = I;
> > +    switch (Node->getOpcode()) {
> > +    // Fix the register class in copy to CopyToReg nodes - ISel will always
> > +    // use SReg classes for 64-bit copies, but this is not always what we want.
> > +    case ISD::CopyToReg: {
> > +      unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
> > +      SDValue Val = Node->getOperand(2);
> > +      const TargetRegisterClass *RC = RegInfo->getRegClass(Reg);
> > +      if (RC != &AMDGPU::SReg_64RegClass) {
> > +        continue;
> > +      }
> > +
> > +      if (!Val.getNode()->isMachineOpcode()) {
> > +        continue;
> > +      }
> > +
> > +      const MCInstrDesc Desc = TM.getInstrInfo()->get(Val.getNode()->getMachineOpcode());
> > +      const TargetRegisterInfo *TRI = TM.getRegisterInfo();
> > +      RegInfo->setRegClass(Reg, TRI->getRegClass(Desc.OpInfo[0].RegClass));
> > +      continue;
> > +    }
> > +    }
> > +
> > +    MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
> > +    if (!MachineNode)
> >       continue;
> > 
> > -    SDNode *ResNode = Lowering.PostISelFolding(Node, *CurDAG);
> > -    if (ResNode != Node)
> > +    SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
> > +    if (ResNode != Node) {
> >       ReplaceUses(Node, ResNode);
> > +    }
> >   }
> > }
> > -
> > 
> > 
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




More information about the llvm-commits mailing list