[llvm] r183135 - R600/SI: Adjust some instructions' out register class after ISel

[Rafael Ávila De Espíndola]

Test case?

Sent from my iPhone

On 2013-06-03, at 13:39, Tom Stellard <thomas.stellard at amd.com> wrote:

> Author: tstellar
> Date: Mon Jun  3 12:39:58 2013
> New Revision: 183135
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=183135&view=rev
> Log:
> R600/SI: Adjust some instructions' out register class after ISel
> 
> This is necessary to avoid generating VGPR to SGPR copies in some
> cases.
> 
> Modified:
>    llvm/trunk/lib/Target/R600/SIISelLowering.cpp
>    llvm/trunk/lib/Target/R600/SIISelLowering.h
> 
> Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=183135&r1=183134&r2=183135&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Mon Jun  3 12:39:58 2013
> @@ -809,6 +809,7 @@ void SITargetLowering::adjustWritemask(M
> /// \brief Fold the instructions after slecting them
> SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
>                                           SelectionDAG &DAG) const {
> +  Node = AdjustRegClass(Node, DAG);
> 
>   if (AMDGPU::isMIMG(Node->getMachineOpcode()) != -1)
>     adjustWritemask(Node, DAG);
> @@ -840,3 +841,53 @@ void SITargetLowering::AdjustInstrPostIn
>   MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
>   MRI.setRegClass(VReg, RC);
> }
> +
> +MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
> +                                                SelectionDAG &DAG) const {
> +
> +  SDLoc DL(N);
> +  unsigned NewOpcode = N->getMachineOpcode();
> +
> +  switch (N->getMachineOpcode()) {
> +  default: return N;
> +  case AMDGPU::REG_SEQUENCE: {
> +    // MVT::i128 only use SGPRs, so i128 REG_SEQUENCEs don't need to be
> +    // rewritten.
> +    if (N->getValueType(0) == MVT::i128) {
> +      return N;
> +    }
> +    const SDValue Ops[] = {
> +      DAG.getTargetConstant(AMDGPU::VReg_64RegClassID, MVT::i32),
> +      N->getOperand(1) , N->getOperand(2),
> +      N->getOperand(3), N->getOperand(4)
> +    };
> +    return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::i64, Ops);
> +  }
> +
> +  case AMDGPU::S_LOAD_DWORD_IMM:
> +    NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
> +    // Fall-through
> +  case AMDGPU::S_LOAD_DWORDX2_SGPR:
> +    if (NewOpcode == N->getMachineOpcode()) {
> +      NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
> +    }
> +    // Fall-through
> +  case AMDGPU::S_LOAD_DWORDX4_IMM:
> +  case AMDGPU::S_LOAD_DWORDX4_SGPR: {
> +    if (NewOpcode == N->getMachineOpcode()) {
> +      NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
> +    }
> +    if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
> +      return N;
> +    }
> +    ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
> +    SDValue Ops[] = {
> +      SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
> +                                 DAG.getConstant(0, MVT::i64)), 0),
> +      N->getOperand(0),
> +      DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
> +    };
> +    return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
> +  }
> +  }
> +}
> 
> Modified: llvm/trunk/lib/Target/R600/SIISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.h?rev=183135&r1=183134&r2=183135&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/SIISelLowering.h (original)
> +++ llvm/trunk/lib/Target/R600/SIISelLowering.h Mon Jun  3 12:39:58 2013
> @@ -36,6 +36,7 @@ class SITargetLowering : public AMDGPUTa
> 
>   SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
>   void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
> +  MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
> 
> public:
>   SITargetLowering(TargetMachine &tm);
> 
> 
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