[llvm] r183003 - ARM: fix VEXT encoding corner case

[Tim Northover]

Author: tnorthover
Date: Fri May 31 08:47:25 2013
New Revision: 183003

URL: http://llvm.org/viewvc/llvm-project?rev=183003&view=rev
Log:
ARM: fix VEXT encoding corner case

The disassembly of VEXT instructions was too lax in the bits checked. This
fixes the case where the instruction affects Q-registers but a misaligned lane
was specified (should be UNDEFINED).

Patch by Amaury de la Vieuville

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=183003&r1=183002&r2=183003&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri May 31 08:47:25 2013
@@ -5509,8 +5509,9 @@ class VEXTd<string OpcodeStr, string Dt,
         IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
         [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
                                      (Ty DPR:$Vm), imm:$index)))]> {
-  bits<4> index;
-  let Inst{11-8} = index{3-0};
+  bits<3> index;
+  let Inst{11} = 0b0;
+  let Inst{10-8} = index{2-0};
 }
 
 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
@@ -5525,14 +5526,14 @@ class VEXTq<string OpcodeStr, string Dt,
 }
 
 def VEXTd8  : VEXTd<"vext", "8",  v8i8, imm0_7> {
-  let Inst{11-8} = index{3-0};
+  let Inst{10-8} = index{2-0};
 }
 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
-  let Inst{11-9} = index{2-0};
+  let Inst{10-9} = index{1-0};
   let Inst{8}    = 0b0;
 }
 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
-  let Inst{11-10} = index{1-0};
+  let Inst{10}     = index{0};
   let Inst{9-8}    = 0b00;
 }
 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt?rev=183003&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt Fri May 31 08:47:25 2013
@@ -0,0 +1,5 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding"
+
+# invalid imm4 value (0b1xxx)
+# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
+0x8f 0xf9 0xf7 0xf2