[llvm] r182929 - X86: allow registers 8-15 in test

[Tim Northover]

Author: tnorthover
Date: Thu May 30 08:56:32 2013
New Revision: 182929

URL: http://llvm.org/viewvc/llvm-project?rev=182929&view=rev
Log:
X86: allow registers 8-15 in test

This test was failing on some hosts when an unexpected register was used for a
variable. This just extends the regexp to allow the new x86-64 registers.

Modified:
    llvm/trunk/test/CodeGen/X86/zext-sext.ll

Modified: llvm/trunk/test/CodeGen/X86/zext-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zext-sext.ll?rev=182929&r1=182928&r2=182929&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/zext-sext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/zext-sext.ll Thu May 30 08:56:32 2013
@@ -33,9 +33,9 @@ entry:
   %tmp11 = sext i32 %tmp4 to i64
   %tmp12 = add i64 %tmp11, 5089792279245435153
 
-; CHECK:      addl	$2138875574, %e[[REGISTER_zext:[a-z]+]]
-; CHECK-NEXT: movslq	%e[[REGISTER_zext]], [[REGISTER_tmp:%[a-z]+]]
-; CHECK:      movq	[[REGISTER_tmp]], [[REGISTER_sext:%[a-z]+]]
+; CHECK:      addl	$2138875574, %e[[REGISTER_zext:[a-z0-9]+]]
+; CHECK-NEXT: movslq	%e[[REGISTER_zext]], [[REGISTER_tmp:%r[a-z0-9]+]]
+; CHECK:      movq	[[REGISTER_tmp]], [[REGISTER_sext:%r[a-z0-9]+]]
 ; CHECK-NEXT: subq	%r[[REGISTER_zext]], [[REGISTER_sext]]
 
   %tmp13 = sub i64 %tmp12, 2138875574