[PATCH] Tidy some register classes for ARM and Thumb

[JF Bastien]

I started going down the rabbit hole, and then retreated with what's there.
I don't think there's all that much left to do, but IIRC I added MI
verification for the functions that worked. This patch fixes some more
tests, but I think no other tests started passing with just those fixes.


On Tue, May 28, 2013 at 11:55 AM, Eric Christopher <echristo at gmail.com>wrote:

> Ah, I thought that it was already at that point. None of the smaller
> functions can be added now or just WIP and you'll add it later?
>
> -eric
>
> On Tue, May 28, 2013 at 11:52 AM, JF Bastien <jfb at google.com> wrote:
> > Agreed, it's on my list of things to do. It requires restricting
> definitions
> > according to uses, and sometimes inserting copies when use requirements
> > conflict. The tests should then pass MI verification.
> >
> >
> > On Tue, May 28, 2013 at 11:46 AM, Eric Christopher <echristo at gmail.com>
> > wrote:
> >>
> >> Seems like a good thing to do no?
> >>
> >> -eric
> >>
> >> On Tue, May 28, 2013 at 11:36 AM, JF Bastien <jfb at google.com> wrote:
> >> > Add -verify-machineinstrs to the Thumb tests that don't have it in
> >> > test/CodeGen/ARM/fast-isel*.
> >> >
> >> >
> >> >
> >> >
> >> >
> >> > On Tue, May 28, 2013 at 11:30 AM, Eric Christopher <
> echristo at gmail.com>
> >> > wrote:
> >> >>
> >> >> LGTM. Testcase for where this showed up?
> >> >>
> >> >> -eric
> >> >>
> >> >> On Tue, May 28, 2013 at 10:43 AM, JF Bastien <jfb at google.com> wrote:
> >> >> > Tidy up three places where the register class for ARM and Thumb
> >> >> > wasn't
> >> >> > restrictive enough:
> >> >> >  - No PC dest for reg-reg add/orr/sub.
> >> >> >  - No PC dest for shifts.
> >> >> >  - No PC or SP for Thumb2 reg-imm add.
> >> >> >
> >> >> > I encountered this while combining FastISel with
> >> >> > -verify-machineinstrs.
> >> >> > These instructions defined registers whose classes weren't
> >> >> > restrictive
> >> >> > enough, and the uses failed verification. They're also undefined in
> >> >> > the
> >> >> > ISA,
> >> >> > or would produce code that FastISel wouldn't want. This doesn't fix
> >> >> > the
> >> >> > register class narrowing issue (where uses should restrict
> >> >> > definitions),
> >> >> > and
> >> >> > isn't thorough, but it's a small step in the right direction.
> >> >> >
> >> >> > _______________________________________________
> >> >> > llvm-commits mailing list
> >> >> > llvm-commits at cs.uiuc.edu
> >> >> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >> >> >
> >> >
> >> >
> >
> >
>
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