[llvm] r182307 - [mips] Add (setne $lhs, 0) instruction selection pattern.

[Akira Hatanaka]

Author: ahatanak
Date: Mon May 20 13:18:07 2013
New Revision: 182307

URL: http://llvm.org/viewvc/llvm-project?rev=182307&view=rev
Log:
[mips] Add (setne $lhs, 0) instruction selection pattern.


Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
    llvm/trunk/test/CodeGen/Mips/setcc-se.ll

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=182307&r1=182306&r2=182307&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon May 20 13:18:07 2013
@@ -1282,6 +1282,8 @@ multiclass SeteqPats<RegisterClass RC, I
                      Instruction SLTuOp, Register ZEROReg> {
   def : MipsPat<(seteq RC:$lhs, 0),
                 (SLTiuOp RC:$lhs, 1)>;
+  def : MipsPat<(setne RC:$lhs, 0),
+                (SLTuOp ZEROReg, RC:$lhs)>;
   def : MipsPat<(seteq RC:$lhs, RC:$rhs),
                 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
   def : MipsPat<(setne RC:$lhs, RC:$rhs),

Modified: llvm/trunk/test/CodeGen/Mips/setcc-se.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setcc-se.ll?rev=182307&r1=182306&r2=182307&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setcc-se.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setcc-se.ll Mon May 20 13:18:07 2013
@@ -9,3 +9,13 @@ entry:
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
+
+; CHECK: setne0:
+; CHECK: sltu ${{[0-9]+}}, $zero, $4
+
+define i32 @setne0(i32 %a) {
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}