[llvm] r182225 - Don't use %g0 to materialize 0 directly.

[Jakob Stoklund Olesen]

Author: stoklund
Date: Sun May 19 16:47:13 2013
New Revision: 182225

URL: http://llvm.org/viewvc/llvm-project?rev=182225&view=rev
Log:
Don't use %g0 to materialize 0 directly.

The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

Modified:
    llvm/trunk/lib/Target/Sparc/README.txt
    llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td
    llvm/trunk/test/CodeGen/SPARC/64bit.ll
    llvm/trunk/test/CodeGen/SPARC/64cond.ll

Modified: llvm/trunk/lib/Target/Sparc/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/README.txt?rev=182225&r1=182224&r2=182225&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/README.txt (original)
+++ llvm/trunk/lib/Target/Sparc/README.txt Sun May 19 16:47:13 2013
@@ -57,3 +57,5 @@ int %t1(int %a, int %b) {
 * Fill delay slots
 
 * Implement JIT support
+
+* Use %g0 directly to materialize 0. No instruction is required.

Modified: llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td?rev=182225&r1=182224&r2=182225&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td Sun May 19 16:47:13 2013
@@ -59,10 +59,6 @@ defm SRAX : F3_S<"srax", 0b100111, 1, sr
 // preferable to use a constant pool load instead, depending on the
 // microarchitecture.
 
-// The %g0 register is constant 0.
-// This is useful for stx %g0, [...], for example.
-def : Pat<(i64 0), (i64 G0)>, Requires<[Is64Bit]>;
-
 // Single-instruction patterns.
 
 // The ALU instructions want their simm13 operands as i32 immediates.

Modified: llvm/trunk/test/CodeGen/SPARC/64bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/64bit.ll?rev=182225&r1=182224&r2=182225&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/64bit.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/64bit.ll Sun May 19 16:47:13 2013
@@ -26,7 +26,7 @@ define i64 @sra_reg(i64 %a, i64 %b) {
 ;     restore %g0, %g0, %o0
 ;
 ; CHECK: ret_imm0
-; CHECK: or %g0, %g0, %i0
+; CHECK: or %g0, 0, %i0
 define i64 @ret_imm0() {
   ret i64 0
 }

Modified: llvm/trunk/test/CodeGen/SPARC/64cond.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/64cond.ll?rev=182225&r1=182224&r2=182225&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/64cond.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/64cond.ll Sun May 19 16:47:13 2013
@@ -98,3 +98,14 @@ entry:
   %rv = select i1 %tobool, double %a, double %b
   ret double %rv
 }
+
+; The MOVXCC instruction can't use %g0 for its tied operand.
+; CHECK: select_consti64_xcc
+; CHECK: subcc
+; CHECK: movg %xcc, 123, %i0
+define i64 @select_consti64_xcc(i64 %x, i64 %y) {
+entry:
+  %tobool = icmp sgt i64 %x, %y
+  %rv = select i1 %tobool, i64 123, i64 0
+  ret i64 %rv
+}