[llvm] r182122 - R600: Factorize Fetch size limit inside AMDGPUSubTarget

[Matt Beaumont-Gay]

On Fri, May 17, 2013 at 9:49 AM, Vincent Lejeune <vljn at ovi.com> wrote:
> Author: vljn
> Date: Fri May 17 11:49:55 2013
> New Revision: 182122
>
> URL: http://llvm.org/viewvc/llvm-project?rev=182122&view=rev
> Log:
> R600: Factorize Fetch size limit inside AMDGPUSubTarget
>
> Modified:
>     llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp
>     llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h
>     llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp
>     llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp?rev=182122&r1=182121&r2=182122&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp Fri May 17 11:49:55 2013
> @@ -37,6 +37,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringR
>    ParseSubtargetFeatures(GPU, FS);
>    DevName = GPU;
>    Device = AMDGPUDeviceInfo::getDeviceFromName(DevName, this, Is64bit);
> +  TexVTXClauseSize = (Device->getGeneration() >= AMDGPUDeviceInfo::HD4XXX)?16:8;

Style nit: Spaces around '?' and ':', please.

>  }
>
>  AMDGPUSubtarget::~AMDGPUSubtarget() {
> @@ -57,6 +58,10 @@ bool
>  AMDGPUSubtarget::hasVertexCache() const {
>    return HasVertexCache;
>  }
> +short
> +AMDGPUSubtarget::getTexVTXClauseSize() const {
> +  return TexVTXClauseSize;
> +}
>  bool
>  AMDGPUSubtarget::isTargetELF() const {
>    return false;
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h?rev=182122&r1=182121&r2=182122&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h Fri May 17 11:49:55 2013
> @@ -37,6 +37,7 @@ private:
>    bool DumpCode;
>    bool R600ALUInst;
>    bool HasVertexCache;
> +  short TexVTXClauseSize;
>
>    InstrItineraryData InstrItins;
>
> @@ -50,6 +51,7 @@ public:
>    bool isOverride(AMDGPUDeviceInfo::Caps) const;
>    bool is64bit() const;
>    bool hasVertexCache() const;
> +  short getTexVTXClauseSize() const;
>
>    // Helper functions to simplify if statements
>    bool isTargetELF() const;
>
> Modified: llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp?rev=182122&r1=182121&r2=182122&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp (original)
> +++ llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp Fri May 17 11:49:55 2013
> @@ -148,7 +148,7 @@ private:
>      for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
>        if (IsTrivialInst(I))
>          continue;
> -      if (AluInstCount > MaxFetchInst)
> +      if (AluInstCount >= MaxFetchInst)
>          break;
>        if ((IsTex && !TII->usesTextureCache(I)) ||
>            (!IsTex && !TII->usesVertexCache(I)))
> @@ -316,10 +316,7 @@ public:
>      TRI(TII->getRegisterInfo()),
>      ST(tm.getSubtarget<AMDGPUSubtarget>()) {
>        const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
> -      if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD4XXX)
> -        MaxFetchInst = 8;
> -      else
> -        MaxFetchInst = 16;
> +      MaxFetchInst = ST.getTexVTXClauseSize();
>    }
>
>    virtual bool runOnMachineFunction(MachineFunction &MF) {
>
> Modified: llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp?rev=182122&r1=182121&r2=182122&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp (original)
> +++ llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp Fri May 17 11:49:55 2013
> @@ -41,11 +41,7 @@ void R600SchedStrategy::initialize(Sched
>
>
>    const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
> -  if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD5XXX) {
> -    InstKindLimit[IDFetch] = 7; // 8 minus 1 for security
> -  } else {
> -    InstKindLimit[IDFetch] = 15; // 16 minus 1 for security
> -  }
> +  InstKindLimit[IDFetch] = ST.getTexVTXClauseSize();
>  }
>
>  void R600SchedStrategy::MoveUnits(ReadyQueue *QSrc, ReadyQueue *QDst)
> @@ -67,9 +63,9 @@ SUnit* R600SchedStrategy::pickNode(bool
>
>    // check if we might want to switch current clause type
>    bool AllowSwitchToAlu = (CurInstKind == IDOther) ||
> -      (CurEmitted > InstKindLimit[CurInstKind]) ||
> +      (CurEmitted >= InstKindLimit[CurInstKind]) ||
>        (Available[CurInstKind]->empty());
> -  bool AllowSwitchFromAlu = (CurEmitted > InstKindLimit[CurInstKind]) &&
> +  bool AllowSwitchFromAlu = (CurEmitted >= InstKindLimit[CurInstKind]) &&
>        (!Available[IDFetch]->empty() || !Available[IDOther]->empty());
>
>    if ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
> @@ -77,7 +73,7 @@ SUnit* R600SchedStrategy::pickNode(bool
>      // try to pick ALU
>      SU = pickAlu();
>      if (SU) {
> -      if (CurEmitted >  InstKindLimit[IDAlu])
> +      if (CurEmitted >= InstKindLimit[IDAlu])
>          CurEmitted = 0;
>        NextInstKind = IDAlu;
>      }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits