[llvm] r182130 - R600: Lower int_load_input to copyFromReg instead of Register node
Vincent Lejeune
vljn at ovi.com
Fri May 17 09:51:06 PDT 2013
Author: vljn
Date: Fri May 17 11:51:06 2013
New Revision: 182130
URL: http://llvm.org/viewvc/llvm-project?rev=182130&view=rev
Log:
R600: Lower int_load_input to copyFromReg instead of Register node
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.
Added:
llvm/trunk/test/CodeGen/R600/load-input-fold.ll
Modified:
llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
Modified: llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ISelLowering.cpp?rev=182130&r1=182129&r2=182130&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/R600ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/R600ISelLowering.cpp Fri May 17 11:51:06 2013
@@ -530,7 +530,11 @@ SDValue R600TargetLowering::LowerOperati
case AMDGPUIntrinsic::R600_load_input: {
int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
- return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ MRI.addLiveIn(Reg);
+ return DAG.getCopyFromReg(DAG.getEntryNode(),
+ DAG.getEntryNode().getDebugLoc(), Reg, VT);
}
case AMDGPUIntrinsic::R600_interp_input: {
Added: llvm/trunk/test/CodeGen/R600/load-input-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/load-input-fold.ll?rev=182130&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/load-input-fold.ll (added)
+++ llvm/trunk/test/CodeGen/R600/load-input-fold.ll Fri May 17 11:51:06 2013
@@ -0,0 +1,121 @@
+;RUN: llc < %s -march=r600 -mcpu=cayman
+;REQUIRES: asserts
+
+define void @main() #0 {
+main_body:
+ %0 = call float @llvm.R600.load.input(i32 4)
+ %1 = call float @llvm.R600.load.input(i32 5)
+ %2 = call float @llvm.R600.load.input(i32 6)
+ %3 = call float @llvm.R600.load.input(i32 7)
+ %4 = call float @llvm.R600.load.input(i32 8)
+ %5 = call float @llvm.R600.load.input(i32 9)
+ %6 = call float @llvm.R600.load.input(i32 10)
+ %7 = call float @llvm.R600.load.input(i32 11)
+ %8 = call float @llvm.R600.load.input(i32 12)
+ %9 = call float @llvm.R600.load.input(i32 13)
+ %10 = call float @llvm.R600.load.input(i32 14)
+ %11 = call float @llvm.R600.load.input(i32 15)
+ %12 = load <4 x float> addrspace(8)* null
+ %13 = extractelement <4 x float> %12, i32 0
+ %14 = fmul float %0, %13
+ %15 = load <4 x float> addrspace(8)* null
+ %16 = extractelement <4 x float> %15, i32 1
+ %17 = fmul float %0, %16
+ %18 = load <4 x float> addrspace(8)* null
+ %19 = extractelement <4 x float> %18, i32 2
+ %20 = fmul float %0, %19
+ %21 = load <4 x float> addrspace(8)* null
+ %22 = extractelement <4 x float> %21, i32 3
+ %23 = fmul float %0, %22
+ %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %25 = extractelement <4 x float> %24, i32 0
+ %26 = fmul float %1, %25
+ %27 = fadd float %26, %14
+ %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %29 = extractelement <4 x float> %28, i32 1
+ %30 = fmul float %1, %29
+ %31 = fadd float %30, %17
+ %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %33 = extractelement <4 x float> %32, i32 2
+ %34 = fmul float %1, %33
+ %35 = fadd float %34, %20
+ %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %37 = extractelement <4 x float> %36, i32 3
+ %38 = fmul float %1, %37
+ %39 = fadd float %38, %23
+ %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %41 = extractelement <4 x float> %40, i32 0
+ %42 = fmul float %2, %41
+ %43 = fadd float %42, %27
+ %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %45 = extractelement <4 x float> %44, i32 1
+ %46 = fmul float %2, %45
+ %47 = fadd float %46, %31
+ %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %49 = extractelement <4 x float> %48, i32 2
+ %50 = fmul float %2, %49
+ %51 = fadd float %50, %35
+ %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %53 = extractelement <4 x float> %52, i32 3
+ %54 = fmul float %2, %53
+ %55 = fadd float %54, %39
+ %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+ %57 = extractelement <4 x float> %56, i32 0
+ %58 = fmul float %3, %57
+ %59 = fadd float %58, %43
+ %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+ %61 = extractelement <4 x float> %60, i32 1
+ %62 = fmul float %3, %61
+ %63 = fadd float %62, %47
+ %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+ %65 = extractelement <4 x float> %64, i32 2
+ %66 = fmul float %3, %65
+ %67 = fadd float %66, %51
+ %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+ %69 = extractelement <4 x float> %68, i32 3
+ %70 = fmul float %3, %69
+ %71 = fadd float %70, %55
+ %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+ %73 = extractelement <4 x float> %72, i32 0
+ %74 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+ %75 = extractelement <4 x float> %74, i32 1
+ %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+ %77 = extractelement <4 x float> %76, i32 2
+ %78 = insertelement <4 x float> undef, float %4, i32 0
+ %79 = insertelement <4 x float> %78, float %5, i32 1
+ %80 = insertelement <4 x float> %79, float %6, i32 2
+ %81 = insertelement <4 x float> %80, float 0.000000e+00, i32 3
+ %82 = insertelement <4 x float> undef, float %73, i32 0
+ %83 = insertelement <4 x float> %82, float %75, i32 1
+ %84 = insertelement <4 x float> %83, float %77, i32 2
+ %85 = insertelement <4 x float> %84, float 0.000000e+00, i32 3
+ %86 = call float @llvm.AMDGPU.dp4(<4 x float> %81, <4 x float> %85)
+ %87 = insertelement <4 x float> undef, float %86, i32 0
+ call void @llvm.R600.store.swizzle(<4 x float> %87, i32 2, i32 2)
+ ret void
+}
+
+; Function Attrs: readnone
+declare float @llvm.R600.load.input(i32) #1
+
+; Function Attrs: readnone
+declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
+
+; Function Attrs: readonly
+declare float @fabs(float) #2
+
+; Function Attrs: readnone
+declare float @llvm.AMDGPU.rsq(float) #1
+
+; Function Attrs: readnone
+declare float @llvm.AMDIL.clamp.(float, float, float) #1
+
+; Function Attrs: nounwind readonly
+declare float @llvm.pow.f32(float, float) #3
+
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+
+attributes #0 = { "ShaderType"="1" }
+attributes #1 = { readnone }
+attributes #2 = { readonly }
+attributes #3 = { nounwind readonly }
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