[llvm] r182113 - R600: Fix encoding for R600 family GPUs

[Tom Stellard]

Hi Bill,

Could you cherry-pick this patch to the 3.3 branch.

Thanks,
Tom


On Fri, May 17, 2013 at 03:23:21PM -0000, Tom Stellard wrote:
> Author: tstellar
> Date: Fri May 17 10:23:21 2013
> New Revision: 182113
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=182113&view=rev
> Log:
> R600: Fix encoding for R600 family GPUs
> 
> Reviewed-by: Vincent Lejeune <vljn at ovi.com>
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=64193
> https://bugs.freedesktop.org/show_bug.cgi?id=64257
> https://bugs.freedesktop.org/show_bug.cgi?id=64320
> 
> NOTE: This is a candidate for the 3.3 branch.
> 
> Added:
>     llvm/trunk/test/CodeGen/R600/r600-encoding.ll
> Modified:
>     llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> 
> Modified: llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp?rev=182113&r1=182112&r2=182113&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp Fri May 17 10:23:21 2013
> @@ -179,6 +179,13 @@ void R600MCCodeEmitter::EncodeInstructio
>      Emit((u_int32_t) 0, OS);
>    } else {
>      uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
> +    if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
> +       ((Desc.TSFlags & R600_InstFlag::OP1) ||
> +         Desc.TSFlags & R600_InstFlag::OP2)) {
> +      uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
> +      Inst &= ~(0x3FFULL << 39);
> +      Inst |= ISAOpCode << 1;
> +    }
>      Emit(Inst, OS);
>    }
>  }
> 
> Added: llvm/trunk/test/CodeGen/R600/r600-encoding.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/r600-encoding.ll?rev=182113&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/r600-encoding.ll (added)
> +++ llvm/trunk/test/CodeGen/R600/r600-encoding.ll Fri May 17 10:23:21 2013
> @@ -0,0 +1,24 @@
> +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
> +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600-CHECK %s
> +
> +; The earliest R600 GPUs have a slightly different encoding than the rest of
> +; the VLIW4/5 GPUs.
> +
> +; EG-CHECK: @test
> +; EG-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]
> +
> +; R600-CHECK: @test
> +; R600-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
> +
> +define void @test() {
> +entry:
> +  %0 = call float @llvm.R600.load.input(i32 0)
> +  %1 = call float @llvm.R600.load.input(i32 1)
> +  %2 = fmul float %0, %1
> +  call void @llvm.AMDGPU.store.output(float %2, i32 0)
> +  ret void
> +}
> +
> +declare float @llvm.R600.load.input(i32) readnone
> +
> +declare void @llvm.AMDGPU.store.output(float, i32)
> 
> 
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