[llvm] r182044 - [mips] Test case for r182042. Add comment.

[Akira Hatanaka]

Author: ahatanak
Date: Thu May 16 14:57:23 2013
New Revision: 182044

URL: http://llvm.org/viewvc/llvm-project?rev=182044&view=rev
Log:
[mips] Test case for r182042. Add comment.


Added:
    llvm/trunk/test/CodeGen/Mips/int-to-float-conversion.ll
Modified:
    llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.h

Modified: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.h?rev=182044&r1=182043&r2=182044&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.h Thu May 16 14:57:23 2013
@@ -83,9 +83,21 @@ private:
 
   void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                    unsigned Opc) const;
+
+  /// Expand pseudo Int-to-FP conversion instructions.
+  ///
+  /// For example, the following pseudo instruction
+  ///  PseudoCVT_D32_W D2, A5
+  /// gets expanded into these two instructions:
+  ///  MTC1 F4, A5
+  ///  CVT_D32_W D2, F4
+  ///
+  /// We do this expansion post-RA to avoid inserting a floating point copy
+  /// instruction between MTC1 and CVT_D32_W.
   void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                       unsigned CvtOpc, unsigned MovOpc, bool DstIsLarger,
                       bool SrcIsLarger, bool IsI64) const;
+
   void expandExtractElementF64(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator I) const;
   void expandBuildPairF64(MachineBasicBlock &MBB,

Added: llvm/trunk/test/CodeGen/Mips/int-to-float-conversion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/int-to-float-conversion.ll?rev=182044&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/int-to-float-conversion.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/int-to-float-conversion.ll Thu May 16 14:57:23 2013
@@ -0,0 +1,48 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
+
+ at i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
+ at i3 = common global i32* null, align 4
+
+; 32: test_float_int_:
+; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]
+
+define float @test_float_int_(i32 %a) {
+entry:
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+; 32: test_double_int_:
+; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 32: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
+; 64: test_double_int_:
+; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 64: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
+
+define double @test_double_int_(i32 %a) {
+entry:
+  %conv = sitofp i32 %a to double
+  ret double %conv
+}
+
+; 64: test_float_LL_:
+; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 64: cvt.s.l $f{{[0-9]+}}, $f[[R0]]
+
+define float @test_float_LL_(i64 %a) {
+entry:
+  %conv = sitofp i64 %a to float
+  ret float %conv
+}
+
+; 64: test_double_LL_:
+; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
+; 64: cvt.d.l $f{{[0-9]+}}, $f[[R0]]
+
+define double @test_double_LL_(i64 %a) {
+entry:
+  %conv = sitofp i64 %a to double
+  ret double %conv
+}