[llvm] r182020 - Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll

[Bill Schmidt]

Author: wschmidt
Date: Thu May 16 11:15:18 2013
New Revision: 182020

URL: http://llvm.org/viewvc/llvm-project?rev=182020&view=rev
Log:
Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll

While testing some experimental code to add vector-scalar registers to
PowerPC, I noticed that a couple of independent instructions were
flipped by the scheduler.  The new CHECK-DAG support is perfect for
avoiding this problem.

Modified:
    llvm/trunk/test/CodeGen/PowerPC/recipest.ll

Modified: llvm/trunk/test/CodeGen/PowerPC/recipest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/recipest.ll?rev=182020&r1=182019&r2=182020&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/recipest.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/recipest.ll Thu May 16 11:15:18 2013
@@ -14,8 +14,8 @@ entry:
   ret double %r
 
 ; CHECK: @foo
-; CHECK: frsqrte
-; CHECK: fnmsub
+; CHECK-DAG: frsqrte
+; CHECK-DAG: fnmsub
 ; CHECK: fmul
 ; CHECK: fmadd
 ; CHECK: fmul
@@ -39,8 +39,8 @@ entry:
   ret double %r
 
 ; CHECK: @foof
-; CHECK: frsqrtes
-; CHECK: fnmsubs
+; CHECK-DAG: frsqrtes
+; CHECK-DAG: fnmsubs
 ; CHECK: fmuls
 ; CHECK: fmadds
 ; CHECK: fmuls
@@ -61,8 +61,8 @@ entry:
   ret float %r
 
 ; CHECK: @foo
-; CHECK: frsqrte
-; CHECK: fnmsub
+; CHECK-DAG: frsqrte
+; CHECK-DAG: fnmsub
 ; CHECK: fmul
 ; CHECK: fmadd
 ; CHECK: fmul
@@ -86,8 +86,8 @@ entry:
   ret float %r
 
 ; CHECK: @goo
-; CHECK: frsqrtes
-; CHECK: fnmsubs
+; CHECK-DAG: frsqrtes
+; CHECK-DAG: fnmsubs
 ; CHECK: fmuls
 ; CHECK: fmadds
 ; CHECK: fmuls
@@ -120,8 +120,8 @@ entry:
   ret double %r
 
 ; CHECK: @foo2
-; CHECK: fre
-; CHECK: fnmsub
+; CHECK-DAG: fre
+; CHECK-DAG: fnmsub
 ; CHECK: fmadd
 ; CHECK: fnmsub
 ; CHECK: fmadd
@@ -139,8 +139,8 @@ entry:
   ret float %r
 
 ; CHECK: @goo2
-; CHECK: fres
-; CHECK: fnmsubs
+; CHECK-DAG: fres
+; CHECK-DAG: fnmsubs
 ; CHECK: fmadds
 ; CHECK: fmuls
 ; CHECK: blr
@@ -169,8 +169,8 @@ entry:
   ret double %r
 
 ; CHECK: @foo3
-; CHECK: frsqrte
-; CHECK: fnmsub
+; CHECK-DAG: frsqrte
+; CHECK-DAG: fnmsub
 ; CHECK: fmul
 ; CHECK: fmadd
 ; CHECK: fmul
@@ -195,8 +195,8 @@ entry:
   ret float %r
 
 ; CHECK: @goo3
-; CHECK: frsqrtes
-; CHECK: fnmsubs
+; CHECK-DAG: frsqrtes
+; CHECK-DAG: fnmsubs
 ; CHECK: fmuls
 ; CHECK: fmadds
 ; CHECK: fmuls