[llvm] r181225 - R600: Stop emitting the instruction type byte before each instruction
Tom Stellard
thomas.stellard at amd.com
Mon May 6 10:50:44 PDT 2013
Author: tstellar
Date: Mon May 6 12:50:44 2013
New Revision: 181225
URL: http://llvm.org/viewvc/llvm-project?rev=181225&view=rev
Log:
R600: Stop emitting the instruction type byte before each instruction
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
Tested-By: Aaron Watry <awatry at gmail.com>
Modified:
llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
llvm/trunk/test/CodeGen/R600/call_fs.ll
llvm/trunk/test/CodeGen/R600/cf_end.ll
Modified: llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp?rev=181225&r1=181224&r2=181225&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp Mon May 6 12:50:44 2013
@@ -9,12 +9,8 @@
//
/// \file
///
-/// This code emitter outputs bytecode that is understood by the r600g driver
-/// in the Mesa [1] project. The bytecode is very similar to the hardware's ISA,
-/// but it still needs to be run through a finalizer in order to be executed
-/// by the GPU.
-///
-/// [1] http://www.mesa3d.org/
+/// \brief The R600 code emitter produces machine code that can be executed
+/// directly on the GPU device.
//
//===----------------------------------------------------------------------===//
@@ -95,16 +91,6 @@ enum RegElement {
ELEMENT_W
};
-enum InstrTypes {
- INSTR_ALU = 0,
- INSTR_TEX,
- INSTR_FC,
- INSTR_NATIVE,
- INSTR_VTX,
- INSTR_EXPORT,
- INSTR_CFALU
-};
-
enum FCInstr {
FC_IF_PREDICATE = 0,
FC_ELSE,
@@ -152,7 +138,6 @@ void R600MCCodeEmitter::EncodeInstructio
case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
- EmitByte(INSTR_NATIVE, OS);
Emit(inst, OS);
break;
}
@@ -170,9 +155,7 @@ void R600MCCodeEmitter::EncodeInstructio
uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
InstWord2 |= 1 << 19;
- EmitByte(INSTR_NATIVE, OS);
Emit(InstWord01, OS);
- EmitByte(INSTR_NATIVE, OS);
Emit(InstWord2, OS);
Emit((u_int32_t) 0, OS);
break;
@@ -246,9 +229,7 @@ void R600MCCodeEmitter::EncodeInstructio
SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
Offsets[2] << 10;
- EmitByte(INSTR_NATIVE, OS);
Emit(Word01, OS);
- EmitByte(INSTR_NATIVE, OS);
Emit(Word2, OS);
Emit((u_int32_t) 0, OS);
break;
@@ -256,7 +237,6 @@ void R600MCCodeEmitter::EncodeInstructio
case AMDGPU::CF_ALU:
case AMDGPU::CF_ALU_PUSH_BEFORE: {
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
- EmitByte(INSTR_NATIVE, OS);
Emit(Inst, OS);
break;
}
@@ -289,13 +269,11 @@ void R600MCCodeEmitter::EncodeInstructio
case AMDGPU::CF_END_EG:
case AMDGPU::CF_END_CM: {
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
- EmitByte(INSTR_NATIVE, OS);
Emit(Inst, OS);
break;
}
default:
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
- EmitByte(INSTR_NATIVE, OS);
Emit(Inst, OS);
break;
}
@@ -307,9 +285,6 @@ void R600MCCodeEmitter::EmitALUInstr(con
raw_ostream &OS) const {
const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
- // Emit instruction type
- EmitByte(INSTR_ALU, OS);
-
uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
//older alu have different encoding for instructions with one or two src
@@ -324,8 +299,6 @@ void R600MCCodeEmitter::EmitALUInstr(con
unsigned SrcNum = MCDesc.TSFlags & R600_InstFlag::OP3 ? 3 :
MCDesc.TSFlags & R600_InstFlag::OP2 ? 2 : 1;
- EmitByte(SrcNum, OS);
-
const unsigned SrcOps[3][2] = {
{R600Operands::SRC0, R600Operands::SRC0_SEL},
{R600Operands::SRC1, R600Operands::SRC1_SEL},
@@ -335,7 +308,6 @@ void R600MCCodeEmitter::EmitALUInstr(con
for (unsigned SrcIdx = 0; SrcIdx < SrcNum; ++SrcIdx) {
unsigned RegOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][0]];
unsigned SelOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][1]];
- EmitSrcISA(MI, RegOpIdx, SelOpIdx, OS);
}
Emit(InstWord01, OS);
@@ -446,9 +418,6 @@ void R600MCCodeEmitter::EmitSrcISA(const
void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const {
- // Emit instruction type
- EmitByte(INSTR_FC, OS);
-
// Emit SRC
unsigned NumOperands = MI.getNumOperands();
if (NumOperands > 0) {
Modified: llvm/trunk/test/CodeGen/R600/call_fs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/call_fs.ll?rev=181225&r1=181224&r2=181225&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/call_fs.ll (original)
+++ llvm/trunk/test/CodeGen/R600/call_fs.ll Mon May 6 12:50:44 2013
@@ -3,9 +3,9 @@
; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600-CHECK %s
; EG-CHECK: @call_fs
-; EG-CHECK: CALL_FS ; encoding: [0x03,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x84]
+; EG-CHECK: CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x84]
; R600-CHECK: @call_fs
-; R600-CHECK:CALL_FS ; encoding: [0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89]
+; R600-CHECK:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89]
define void @call_fs() #0 {
Modified: llvm/trunk/test/CodeGen/R600/cf_end.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cf_end.ll?rev=181225&r1=181224&r2=181225&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/cf_end.ll (original)
+++ llvm/trunk/test/CodeGen/R600/cf_end.ll Mon May 6 12:50:44 2013
@@ -2,8 +2,8 @@
; RUN: llc < %s -march=r600 -mcpu=caicos --show-mc-encoding | FileCheck --check-prefix=EG-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=cayman --show-mc-encoding | FileCheck --check-prefix=CM-CHECK %s
-; EG-CHECK: CF_END ; encoding: [0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x80]
-; CM-CHECK: CF_END ; encoding: [0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88]
+; EG-CHECK: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x80]
+; CM-CHECK: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88]
define void @eop() {
ret void
}
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