[llvm] r180871 - Optimize away nop CONCAT_VECTOR nodes.

[Nadav Rotem]

Thanks for catching this bug.  LGTM.  Please commit. 

Thanks,
Nadav

On May 5, 2013, at 8:37 AM, "Kuperstein, Michael M" <michael.m.kuperstein at intel.com> wrote:

> Hi Nadav,
> 
> This breaks a case where a concat_vector has a single non-undef source, but concatenates it with an undef in order to extend the vector. I'm attaching a test-case and a proposed patch. 
> Only ran x86 tests, not ARM, can you check this doesn't break the original issue? If it looks ok, I'll add the test to the patch and commit.
> 
> Thanks,
>   Michael
> 
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Nadav Rotem
> Sent: Wednesday, May 01, 2013 22:19
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r180871 - Optimize away nop CONCAT_VECTOR nodes.
> 
> Author: nadav
> Date: Wed May  1 14:18:51 2013
> New Revision: 180871
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=180871&view=rev
> Log:
> Optimize away nop CONCAT_VECTOR nodes.
> 
> Optimize CONCAT_VECTOR nodes that merge EXTRACT_SUBVECTOR values that extract from the same vector.
> 
> rdar://13402653
> PR15866
> 
> 
> Added:
>    llvm/trunk/test/CodeGen/ARM/nop_concat_vectors.ll
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=180871&r1=180870&r2=180871&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed May  1 
> +++ 14:18:51 2013
> @@ -9122,6 +9122,45 @@ SDValue DAGCombiner::visitCONCAT_VECTORS
>   if (ISD::allOperandsUndef(N))
>     return DAG.getUNDEF(N->getValueType(0));
> 
> +  // Type legalization of vectors and DAG canonicalization of 
> + SHUFFLE_VECTOR  // nodes often generate nop CONCAT_VECTOR nodes.
> +  // Scan the CONCAT_VECTOR operands and look for a CONCAT operations 
> + that  // place the incoming vectors at the exact same location.
> +  SDValue SingleSource = SDValue();
> +  unsigned PartNumElem = 
> + N->getOperand(0).getValueType().getVectorNumElements();
> +
> +  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
> +    SDValue Op = N->getOperand(i);
> +
> +    if (Op.getOpcode() == ISD::UNDEF)
> +      continue;
> +
> +    // Check if this is the identity extract:
> +    if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
> +      return SDValue();
> +
> +    // Find the single incoming vector for the extract_subvector.
> +    if (SingleSource.getNode()) {
> +      if (Op.getOperand(0) != SingleSource)
> +        return SDValue();
> +    } else {
> +      SingleSource = Op.getOperand(0);
> +    }
> +
> +    unsigned IdentityIndex = i * PartNumElem;
> +    ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
> +    // The extract index must be constant.
> +    if (!CS)
> +      return SDValue();
> +    
> +    // Check that we are reading from the identity index.
> +    if (CS->getZExtValue() != IdentityIndex)
> +      return SDValue();
> +  }
> +
> +  if (SingleSource.getNode())
> +    return SingleSource;
> +  
>   return SDValue();
> }
> 
> 
> Added: llvm/trunk/test/CodeGen/ARM/nop_concat_vectors.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/nop_concat_vectors.ll?rev=180871&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/nop_concat_vectors.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/nop_concat_vectors.ll Wed May  1 
> +++ 14:18:51 2013
> @@ -0,0 +1,13 @@
> +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
> +
> +;CHECK: _foo
> +;CHECK-NOT: vld1.32
> +;CHECK-NOT: vst1.32
> +;CHECK: bx
> +define void @foo(<16 x i8>* %J) {
> +  %A = load <16 x i8>* %J
> +  %T1 = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 8, 
> +i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
> +  %T2 = shufflevector <8 x i8>  %T1, <8 x i8> undef, <16 x i32> <i32 
> +undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 
> +undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 
> +7>
> +  store <16 x i8> %T2, <16 x i8>* %J
> +  ret void
> +}
> 
> 
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