[llvm] r180758 - R600: Add a Bank Swizzle operand
Rafael Espíndola
rafael.espindola at gmail.com
Mon Apr 29 18:50:53 PDT 2013
test?
On 29 April 2013 20:14, Vincent Lejeune <vljn at ovi.com> wrote:
> Author: vljn
> Date: Mon Apr 29 19:14:08 2013
> New Revision: 180758
>
> URL: http://llvm.org/viewvc/llvm-project?rev=180758&view=rev
> Log:
> R600: Add a Bank Swizzle operand
>
> Modified:
> llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> llvm/trunk/lib/Target/R600/R600Defines.h
> llvm/trunk/lib/Target/R600/R600InstrInfo.cpp
> llvm/trunk/lib/Target/R600/R600Instructions.td
>
> Modified: llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp?rev=180758&r1=180757&r2=180758&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp Mon Apr 29 19:14:08 2013
> @@ -428,7 +428,7 @@ void R600MCCodeEmitter::EmitSrcISA(const
> }
>
> if (Reg == AMDGPU::ALU_LITERAL_X) {
> - unsigned ImmOpIndex = MI.getNumOperands() - 1;
> + unsigned ImmOpIndex = MI.getNumOperands() - 2;
> MCOperand ImmOp = MI.getOperand(ImmOpIndex);
> if (ImmOp.isFPImm()) {
> InlineConstant.f = ImmOp.getFPImm();
>
> Modified: llvm/trunk/lib/Target/R600/R600Defines.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600Defines.h?rev=180758&r1=180757&r2=180758&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600Defines.h (original)
> +++ llvm/trunk/lib/Target/R600/R600Defines.h Mon Apr 29 19:14:08 2013
> @@ -80,6 +80,7 @@ namespace R600Operands {
> LAST,
> PRED_SEL,
> IMM,
> + BANK_SWIZZLE,
> COUNT
> };
>
> @@ -87,11 +88,11 @@ namespace R600Operands {
> // W C S S S S S S S S S S S
> // R O D L S R R R R S R R R R S R R R L P
> // D U I M R A R C C C C R C C C C R C C C A R I
> -// S E U T O E M C 0 0 0 0 C 1 1 1 1 C 2 2 2 S E M
> -// T M P E D L P 0 N R A S 1 N R A S 2 N R S T D M
> - {0,-1,-1, 1, 2, 3, 4, 5, 6, 7, 8, 9,-1,-1,-1,-1,-1,-1,-1,-1,-1,10,11,12},
> - {0, 1, 2, 3, 4 ,5 ,6 ,7, 8, 9,10,11,12,13,14,15,16,-1,-1,-1,-1,17,18,19},
> - {0,-1,-1,-1,-1, 1, 2, 3, 4, 5,-1, 6, 7, 8, 9,-1,10,11,12,13,14,15,16,17}
> +// S E U T O E M C 0 0 0 0 C 1 1 1 1 C 2 2 2 S E M B
> +// T M P E D L P 0 N R A S 1 N R A S 2 N R S T D M S
> + {0,-1,-1, 1, 2, 3, 4, 5, 6, 7, 8, 9,-1,-1,-1,-1,-1,-1,-1,-1,-1,10,11,12,13},
> + {0, 1, 2, 3, 4 ,5 ,6 ,7, 8, 9,10,11,12,13,14,15,16,-1,-1,-1,-1,17,18,19,20},
> + {0,-1,-1,-1,-1, 1, 2, 3, 4, 5,-1, 6, 7, 8, 9,-1,10,11,12,13,14,15,16,17,18}
> };
>
> }
>
> Modified: llvm/trunk/lib/Target/R600/R600InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600InstrInfo.cpp?rev=180758&r1=180757&r2=180758&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/R600/R600InstrInfo.cpp Mon Apr 29 19:14:08 2013
> @@ -702,7 +702,8 @@ MachineInstrBuilder R600InstrInfo::build
> //scheduling to the backend, we can change the default to 0.
> MIB.addImm(1) // $last
> .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
> - .addImm(0); // $literal
> + .addImm(0) // $literal
> + .addImm(0); // $bank_swizzle
>
> return MIB;
> }
>
> Modified: llvm/trunk/lib/Target/R600/R600Instructions.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600Instructions.td?rev=180758&r1=180757&r2=180758&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600Instructions.td (original)
> +++ llvm/trunk/lib/Target/R600/R600Instructions.td Mon Apr 29 19:14:08 2013
> @@ -75,6 +75,9 @@ class InstFlag<string PM = "printOperand
> def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
> let PrintMethod = "printSel";
> }
> +def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
> + let PrintMethod = "printSel";
> +}
>
> def LITERAL : InstFlag<"printLiteral">;
>
> @@ -138,7 +141,7 @@ class R600ALU_Word1 {
> field bits<32> Word1;
>
> bits<11> dst;
> - bits<3> bank_swizzle = 0;
> + bits<3> bank_swizzle;
> bits<1> dst_rel;
> bits<1> clamp;
>
> @@ -350,7 +353,8 @@ class R600_1OP <bits<11> inst, string op
> InstR600 <(outs R600_Reg32:$dst),
> (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
> R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
> - LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
> + LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
> + BANK_SWIZZLE:$bank_swizzle),
> !strconcat(" ", opName,
> "$clamp $dst$write$dst_rel$omod, "
> "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
> @@ -390,7 +394,8 @@ class R600_2OP <bits<11> inst, string op
> OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
> R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
> R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
> - LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
> + LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
> + BANK_SWIZZLE:$bank_swizzle),
> !strconcat(" ", opName,
> "$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
> "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
> @@ -427,7 +432,8 @@ class R600_3OP <bits<5> inst, string opN
> R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
> R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
> R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
> - LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
> + LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
> + BANK_SWIZZLE:$bank_swizzle),
> !strconcat(" ", opName, "$clamp $dst$dst_rel, "
> "$src0_neg$src0$src0_rel, "
> "$src1_neg$src1$src1_rel, "
>
>
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