[RFC v3] PowerPC asm parser

[Ulrich Weigand]

Hello,

while there's still two pre-requisite patches outstanding:

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130422/172665.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130422/172778.html

I though it would be a good idea to post another iteration of the asm
parser patches.

The main differences to the previous revisions are:

- Enable for powerpc as well as powerpc64 targets
(Note that assembler still doesn't verify feature sets, so it will happily
assemble 64-bit instructions even when called in powerpc mode, and will
accept any instruction it understands even when called with a more
restrictive -march setting.)

- Support %r1 style register names (as requested by Roman)

- Add some test cases
The tests currently cover all instructions from the following PowerPC ISA
v2.06 Book I facilities: Branch, Fixed-point, Floating-Point, and Vector.
In addition, the tests cover all Book I extended mnemonics and the Book II
storage control instructions (including extended mnemonics).  Note that a
number of instructions are not yet supported by the back-end; I've added
them to the tests anyway, but commented out with a FIXME.

Also note that running the tests uncovered yet more instances of wrong
encodings; I've checked in fixes for those earlier today.


Any comments welcome!

Bye,
Ulrich


(See attached file: diff-llvm-asm-parser)
(See attached file: diff-llvm-asm-aliases)
(See attached file: diff-llvm-asm-inline)
(See attached file: diff-llvm-asm-variants)
(See attached file: diff-llvm-asm-dollar)
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