[PATCH 2/2] R600: Use new tablegen syntax for patterns

[Michel Dänzer]

On Thu, 2013-04-25 at 13:13 -0400, Tom Stellard wrote:
> From: Christian König <christian.koenig at amd.com>
> 
> All but two patterns have been converted to the new syntax.  The
> remaining two patterns will require COPY_TO_REGCLASS instructions, which
> the VLIW DAG Scheduler cannot handle.

The SI changes look good to me, just one minor thing:


> @@ -1520,30 +1509,33 @@ def : Pat <
>  /**********   VOP3 Patterns    **********/
>  /********** ================== **********/
>  
> -def : Pat <(f32 (fadd (fmul VSrc_32:$src0, VSrc_32:$src1), VSrc_32:$src2)),
> -           (V_MAD_F32 VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2)>;
> +def : Pat <
> +  (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)),
> +  (V_MAD_F32 $src0, $src1, $src2)
> +>;

Some patterns like this one no longer use any register prefixes in the
output part, but a lot of them still do. Should they be removed from all
patterns? Could always be done in a followup change though.


-- 
Earthling Michel Dänzer           |                   http://www.amd.com
Libre software enthusiast         |          Debian, X and DRI developer