[llvm] r180040 - 80 columns.

[Akira Hatanaka]

Author: ahatanak
Date: Mon Apr 22 15:13:37 2013
New Revision: 180040

URL: http://llvm.org/viewvc/llvm-project?rev=180040&view=rev
Log:
80 columns.

Modified:
    llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsOs16.cpp
    llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp?rev=180040&r1=180039&r2=180040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16ISelLowering.cpp Mon Apr 22 15:13:37 2013
@@ -613,7 +613,8 @@ MachineBasicBlock
   unsigned regX = MI->getOperand(0).getReg();
   unsigned regY = MI->getOperand(1).getReg();
   MachineBasicBlock *target = MI->getOperand(2).getMBB();
-  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
+  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
+    .addReg(regY);
   BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
   MI->eraseFromParent();   // The pseudo instruction is gone now.
   return BB;
@@ -635,7 +636,8 @@ MachineBasicBlock *Mips16TargetLowering:
     CmpOpc = CmpiXOpc;
   else
     llvm_unreachable("immediate field not usable");
-  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
+  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
+    .addImm(imm);
   BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
   MI->eraseFromParent();   // The pseudo instruction is gone now.
   return BB;

Modified: llvm/trunk/lib/Target/Mips/MipsOs16.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsOs16.cpp?rev=180040&r1=180039&r2=180040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsOs16.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsOs16.cpp Mon Apr 22 15:13:37 2013
@@ -1,4 +1,4 @@
-//===---- MipsOs16.cpp for Mips Option -Os16                         --------===//
+//===---- MipsOs16.cpp for Mips Option -Os16                       --------===//
 //
 //                     The LLVM Compiler Infrastructure
 //

Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=180040&r1=180039&r2=180040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Mon Apr 22 15:13:37 2013
@@ -131,7 +131,8 @@ SDValue MipsSETargetLowering::LowerOpera
   case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
   case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
   case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
-  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG);
+  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
+                                          DAG);
   case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
   case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
   }
@@ -328,8 +329,8 @@ static SDValue performDSPShiftCombine(un
   BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
 
   if (!BV ||
-      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, EltSize,
-                           !Subtarget->isLittle()) ||
+      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
+                           EltSize,!Subtarget->isLittle()) ||
       (SplatBitSize != EltSize) ||
       !isUIntN(Log2_32(EltSize), SplatValue.getZExtValue()))
     return SDValue();