[llvm] r179833 - Use 'array_lengthof' as possible to avoid magic numbers
Michael Liao
michael.liao at intel.com
Thu Apr 18 21:17:03 PDT 2013
Sure, that's a good idea. - Michael
On Thu, 2013-04-18 at 21:09 -0700, David Blaikie wrote:
> On Thu, Apr 18, 2013 at 9:03 PM, Michael Liao <michael.liao at intel.com> wrote:
> > Author: hliao
> > Date: Thu Apr 18 23:03:37 2013
> > New Revision: 179833
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=179833&view=rev
> > Log:
> > Use 'array_lengthof' as possible to avoid magic numbers
>
> Could you change these APIs to take ArrayRef instead? then it'll
> deduce the length from the array type automatically/correctly.
>
> >
> >
> > Modified:
> > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> >
> > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=179833&r1=179832&r2=179833&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Apr 18 23:03:37 2013
> > @@ -1803,7 +1803,8 @@ X86TargetLowering::LowerCallResult(SDVal
> > if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
> > SDValue Ops[] = { Chain, InFlag };
> > Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
> > - MVT::Other, MVT::Glue, Ops, 2), 1);
> > + MVT::Other, MVT::Glue, Ops,
> > + array_lengthof(Ops)), 1);
> > Val = Chain.getValue(0);
> >
> > // Round the f80 to the right size, which also moves it to the appropriate
> > @@ -4422,13 +4423,15 @@ static SDValue getZeroVector(EVT VT, con
> > if (Subtarget->hasInt256()) { // AVX2
> > SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
> > SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
> > - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
> > + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
> > + array_lengthof(Ops));
> > } else {
> > // 256-bit logic and arithmetic instructions in AVX are all
> > // floating-point, no support for integer ops. Emit fp zeroed vectors.
> > SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
> > SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
> > - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
> > + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
> > + array_lengthof(Ops));
> > }
> > } else
> > llvm_unreachable("Unexpected vector type");
> > @@ -4449,7 +4452,8 @@ static SDValue getOnesVector(MVT VT, boo
> > if (VT.is256BitVector()) {
> > if (HasInt256) { // AVX2
> > SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
> > - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
> > + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
> > + array_lengthof(Ops));
> > } else { // AVX
> > Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
> > Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
> > @@ -5119,7 +5123,8 @@ static SDValue EltsFromConsecutiveLoads(
> > SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
> > SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
> > SDValue ResNode =
> > - DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
> > + DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
> > + array_lengthof(Ops), MVT::i64,
> > LDBase->getPointerInfo(),
> > LDBase->getAlignment(),
> > false/*isVolatile*/, true/*ReadMem*/,
> > @@ -7642,10 +7647,10 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Ch
> >
> > if (InFlag) {
> > SDValue Ops[] = { Chain, TGA, *InFlag };
> > - Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
> > + Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
> > } else {
> > SDValue Ops[] = { Chain, TGA };
> > - Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
> > + Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
> > }
> >
> > // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
> > @@ -7955,7 +7960,7 @@ SDValue X86TargetLowering::LowerShiftPar
> > }
> >
> > SDValue Ops[2] = { Lo, Hi };
> > - return DAG.getMergeValues(Ops, 2, dl);
> > + return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
> > }
> >
> > SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
> > @@ -8238,8 +8243,8 @@ SDValue X86TargetLowering::LowerUINT_TO_
> >
> > SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
> > SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
> > - SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
> > - MVT::i64, MMO);
> > + SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
> > + array_lengthof(Ops), MVT::i64, MMO);
> >
> > APInt FF(32, 0x5F800000ULL);
> >
> > @@ -8331,8 +8336,8 @@ X86TargetLowering:: FP_TO_INTHelper(SDVa
> > MachineMemOperand *MMO =
> > MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
> > MachineMemOperand::MOLoad, MemSize, MemSize);
> > - Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
> > - DstTy, MMO);
> > + Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
> > + array_lengthof(Ops), DstTy, MMO);
> > Chain = Value.getValue(1);
> > SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
> > StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
> > @@ -8346,7 +8351,8 @@ X86TargetLowering:: FP_TO_INTHelper(SDVa
> > // Build the FP_TO_INT*_IN_MEM
> > SDValue Ops[] = { Chain, Value, StackSlot };
> > SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
> > - Ops, 3, DstTy, MMO);
> > + Ops, array_lengthof(Ops), DstTy,
> > + MMO);
> > return std::make_pair(FIST, StackSlot);
> > } else {
> > SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
> > @@ -8358,8 +8364,8 @@ X86TargetLowering:: FP_TO_INTHelper(SDVa
> > MVT::i32, eax.getValue(2));
> > SDValue Ops[] = { eax, edx };
> > SDValue pair = IsReplace
> > - ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
> > - : DAG.getMergeValues(Ops, 2, DL);
> > + ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
> > + : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
> > return std::make_pair(pair, SDValue());
> > }
> > }
> > @@ -10980,7 +10986,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD
> > SDValue(Result.getNode(), 1) };
> > SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
> > DAG.getVTList(Op->getValueType(1), MVT::Glue),
> > - Ops, 4);
> > + Ops, array_lengthof(Ops));
> >
> > // Return { result, isValid, chain }.
> > return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
> > @@ -11278,7 +11284,8 @@ SDValue X86TargetLowering::LowerFLT_ROUN
> > SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
> > SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
> > DAG.getVTList(MVT::Other),
> > - Ops, 2, MVT::i16, MMO);
> > + Ops, array_lengthof(Ops), MVT::i16,
> > + MMO);
> >
> > // Load FP Control Word from stack slot
> > SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
> > @@ -12228,7 +12235,7 @@ static SDValue LowerCMP_SWAP(SDValue Op,
> > SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
> > MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
> > SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
> > - Ops, 5, T, MMO);
> > + Ops, array_lengthof(Ops), T, MMO);
> > SDValue cpOut =
> > DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
> > return cpOut;
> > @@ -12250,7 +12257,7 @@ static SDValue LowerREADCYCLECOUNTER(SDV
> > DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
> > rdx.getValue(1)
> > };
> > - return DAG.getMergeValues(Ops, 2, dl);
> > + return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
> > }
> >
> > SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
> > @@ -12514,7 +12521,7 @@ ReplaceATOMIC_BINARY_64(SDNode *Node, Sm
> > SDValue Ops[] = { Chain, In1, In2L, In2H };
> > SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
> > SDValue Result =
> > - DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
> > + DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
> > cast<MemSDNode>(Node)->getMemOperand());
> > SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
> > Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
> > @@ -12594,7 +12601,8 @@ void X86TargetLowering::ReplaceNodeResul
> > eax.getValue(2));
> > // Use a buildpair to merge the two 32-bit values into a 64-bit one.
> > SDValue Ops[] = { eax, edx };
> > - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
> > + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
> > + array_lengthof(Ops)));
> > Results.push_back(edx.getValue(1));
> > return;
> > }
> > @@ -12633,7 +12641,7 @@ void X86TargetLowering::ReplaceNodeResul
> > unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
> > X86ISD::LCMPXCHG8_DAG;
> > SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
> > - Ops, 3, T, MMO);
> > + Ops, array_lengthof(Ops), T, MMO);
> > SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
> > Regs64bit ? X86::RAX : X86::EAX,
> > HalfT, Result.getValue(1));
> > @@ -15120,7 +15128,8 @@ static SDValue PerformShuffleCombine256(
> > SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
> > SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
> > SDValue ResNode =
> > - DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
> > + DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
> > + array_lengthof(Ops),
> > Ld->getMemoryVT(),
> > Ld->getPointerInfo(),
> > Ld->getAlignment(),
> >
> >
> > _______________________________________________
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> > llvm-commits at cs.uiuc.edu
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