[PATCH] Improvde code quality of vselect

[Michael Liao]

Hi Nadav

This patch addresses different issue from simplify-demanded-bits, where
condition in vselect is simplified regarding to BLEND* only takes the
highest bit. This patch address the issue regarding to the value being
selected not the selector. Says, V := select Cond, A, B. When A, or B or
both of them are all 0s or all 1s. We could exploit the fact that packed
comparison will generated all 0s or 1s in each SIMD lane. Such select
could be reduced to an AND/OR or simply removed.

Yours
- Michael



On Wed, 2013-04-10 at 17:30 -0700, Nadav Rotem wrote:
> Michael, 
> 
> 
> I think that the best way to handle the redundant sign-extending is to
> improve the simplify-demanded-bits optimization.  Last year I added
> some code to optimize the X86::VSELECT using simplify-demanded-bits.
>  Do you know why it does not work ?
> 
> 
> Thanks,
> Nadav
> 
> On Apr 10, 2013, at 4:48 PM, Michael Liao <michael.liao at intel.com>
> wrote:
> 
> > Hi,
> > 
> > As we canonicalize sext from i1 to select in instcomb, it generates
> > redundant code to prepare all 0s and all 1s if we don't take it into
> > account that, in SSE/AVX, packed comparisons output all 0s or 1s in
> > SIMD lanes. The attached patch adds optimization for those cases and
> > transforms select into AND/OR to reduce BLEND pressure when
> > profitable.
> > 
> > Thanks for review
> > - Michael
> > 
> > <0001-Add-optimization-to-leverage-all-0s-1s-produced-by-p.patch>_______________________________________________
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> 
>