[llvm] r179164 - R600/SI: remove image sample writemask
Christian Konig
christian.koenig at amd.com
Wed Apr 10 01:39:01 PDT 2013
Author: ckoenig
Date: Wed Apr 10 03:39:01 2013
New Revision: 179164
URL: http://llvm.org/viewvc/llvm-project?rev=179164&view=rev
Log:
R600/SI: remove image sample writemask
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Modified:
llvm/trunk/lib/Target/R600/SIInstructions.td
llvm/trunk/lib/Target/R600/SIIntrinsics.td
llvm/trunk/test/CodeGen/R600/llvm.SI.sample.ll
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=179164&r1=179163&r2=179164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Wed Apr 10 03:39:01 2013
@@ -1219,49 +1219,48 @@ def : Pat <
/* int_SI_sample for simple 1D texture lookup */
def : Pat <
- (int_SI_sample imm:$writemask, VReg_32:$addr,
- SReg_256:$rsrc, SReg_128:$sampler, imm),
- (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_32:$addr,
+ (int_SI_sample VReg_32:$addr, SReg_256:$rsrc, SReg_128:$sampler, imm),
+ (IMAGE_SAMPLE 0xf, 0, 0, 0, 0, 0, 0, 0, VReg_32:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;
class SamplePattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
ValueType addr_type> : Pat <
- (name imm:$writemask, (addr_type addr_class:$addr),
+ (name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, imm),
- (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
+ (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;
class SampleRectPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
ValueType addr_type> : Pat <
- (name imm:$writemask, (addr_type addr_class:$addr),
+ (name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT),
- (opcode imm:$writemask, 1, 0, 0, 0, 0, 0, 0, addr_class:$addr,
+ (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;
class SampleArrayPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
ValueType addr_type> : Pat <
- (name imm:$writemask, (addr_type addr_class:$addr),
+ (name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, TEX_ARRAY),
- (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
+ (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;
class SampleShadowPattern<Intrinsic name, MIMG opcode,
RegisterClass addr_class, ValueType addr_type> : Pat <
- (name imm:$writemask, (addr_type addr_class:$addr),
+ (name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW),
- (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
+ (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;
class SampleShadowArrayPattern<Intrinsic name, MIMG opcode,
RegisterClass addr_class, ValueType addr_type> : Pat <
- (name imm:$writemask, (addr_type addr_class:$addr),
+ (name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW_ARRAY),
- (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
+ (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;
Modified: llvm/trunk/lib/Target/R600/SIIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIIntrinsics.td?rev=179164&r1=179163&r2=179164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIIntrinsics.td (original)
+++ llvm/trunk/lib/Target/R600/SIIntrinsics.td Wed Apr 10 03:39:01 2013
@@ -19,7 +19,7 @@ let TargetPrefix = "SI", isTarget = 1 in
def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v16i8_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
- class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
+ class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
def int_SI_sample : Sample;
def int_SI_sampleb : Sample;
Modified: llvm/trunk/test/CodeGen/R600/llvm.SI.sample.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.SI.sample.ll?rev=179164&r1=179163&r2=179164&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.SI.sample.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.SI.sample.ll Wed Apr 10 03:39:01 2013
@@ -34,37 +34,37 @@ define void @test(i32 %a1, i32 %a2, i32
%v14 = insertelement <4 x i32> undef, i32 %a4, i32 1
%v15 = insertelement <4 x i32> undef, i32 %a4, i32 2
%v16 = insertelement <4 x i32> undef, i32 %a4, i32 3
- %res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v1,
+ %res1 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v1,
<8 x i32> undef, <4 x i32> undef, i32 1)
- %res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v2,
+ %res2 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v2,
<8 x i32> undef, <4 x i32> undef, i32 2)
- %res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v3,
+ %res3 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v3,
<8 x i32> undef, <4 x i32> undef, i32 3)
- %res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v4,
+ %res4 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v4,
<8 x i32> undef, <4 x i32> undef, i32 4)
- %res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v5,
+ %res5 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v5,
<8 x i32> undef, <4 x i32> undef, i32 5)
- %res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v6,
+ %res6 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v6,
<8 x i32> undef, <4 x i32> undef, i32 6)
- %res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v7,
+ %res7 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v7,
<8 x i32> undef, <4 x i32> undef, i32 7)
- %res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v8,
+ %res8 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v8,
<8 x i32> undef, <4 x i32> undef, i32 8)
- %res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v9,
+ %res9 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v9,
<8 x i32> undef, <4 x i32> undef, i32 9)
- %res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v10,
+ %res10 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v10,
<8 x i32> undef, <4 x i32> undef, i32 10)
- %res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v11,
+ %res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11,
<8 x i32> undef, <4 x i32> undef, i32 11)
- %res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v12,
+ %res12 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v12,
<8 x i32> undef, <4 x i32> undef, i32 12)
- %res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v13,
+ %res13 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v13,
<8 x i32> undef, <4 x i32> undef, i32 13)
- %res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v14,
+ %res14 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v14,
<8 x i32> undef, <4 x i32> undef, i32 14)
- %res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v15,
+ %res15 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v15,
<8 x i32> undef, <4 x i32> undef, i32 15)
- %res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v16,
+ %res16 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v16,
<8 x i32> undef, <4 x i32> undef, i32 16)
%e1 = extractelement <4 x float> %res1, i32 0
%e2 = extractelement <4 x float> %res2, i32 0
@@ -101,6 +101,6 @@ define void @test(i32 %a1, i32 %a2, i32
ret void
}
-declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone
+declare <4 x float> @llvm.SI.sample.(<4 x i32>, <8 x i32>, <4 x i32>, i32) readnone
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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