[PATCH] [RFC]TILE-Gx: updated patch for final review
Jiong Wang
jiwang at tilera.com
Tue Apr 9 06:29:32 PDT 2013
on 2013/4/2 23:03, Jiong. Wang wrote:
> on 2013/3/28 0:07, Jiong WANG wrote:
>>
>> 1. rename variable name according to coding style as more as
>> possible.
>>
>> 2. fixed all glitches in regression tests.
>>
>> 3. tried to factor/simplify those code if possible.
>>
>> please review, thanks.
>
> Ping.
Ping ^ 2, Could any gatekeeper have a look at TILE-Gx backend, and give
an explict commit approval?
=== New Updates===
1. interface change:
getTileRegisterNumbering ===> getEncodingValue
2. cleaned byval support code.
---
Regards,
Jiong
>
> ---
> Regards,
> Jiong
> Tilera Corporation.
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
-------------- next part --------------
diff --git a/lib/Target/Tile/MCTargetDesc/TileBaseInfo.h b/lib/Target/Tile/MCTargetDesc/TileBaseInfo.h
index 48b4029..ca07a0a 100644
--- a/lib/Target/Tile/MCTargetDesc/TileBaseInfo.h
+++ b/lib/Target/Tile/MCTargetDesc/TileBaseInfo.h
@@ -120,186 +120,6 @@ enum TileSlotType {
};
}
-// Given the enum value for some register,
-// return the number that it corresponds to.
-inline static unsigned getTileRegisterNumbering(unsigned RegEnum) {
- switch (RegEnum) {
- case Tile::R0:
- case Tile::R0_32:
- return 0;
- case Tile::R1:
- case Tile::R1_32:
- return 1;
- case Tile::R2:
- case Tile::R2_32:
- return 2;
- case Tile::R3:
- case Tile::R3_32:
- return 3;
- case Tile::R4:
- case Tile::R4_32:
- return 4;
- case Tile::R5:
- case Tile::R5_32:
- return 5;
- case Tile::R6:
- case Tile::R6_32:
- return 6;
- case Tile::R7:
- case Tile::R7_32:
- return 7;
- case Tile::R8:
- case Tile::R8_32:
- return 8;
- case Tile::R9:
- case Tile::R9_32:
- return 9;
- case Tile::R10:
- case Tile::R10_32:
- return 10;
- case Tile::R11:
- case Tile::R11_32:
- return 11;
- case Tile::R12:
- case Tile::R12_32:
- return 12;
- case Tile::R13:
- case Tile::R13_32:
- return 13;
- case Tile::R14:
- case Tile::R14_32:
- return 14;
- case Tile::R15:
- case Tile::R15_32:
- return 15;
- case Tile::R16:
- case Tile::R16_32:
- return 16;
- case Tile::R17:
- case Tile::R17_32:
- return 17;
- case Tile::R18:
- case Tile::R18_32:
- return 18;
- case Tile::R19:
- case Tile::R19_32:
- return 19;
- case Tile::R20:
- case Tile::R20_32:
- return 20;
- case Tile::R21:
- case Tile::R21_32:
- return 21;
- case Tile::R22:
- case Tile::R22_32:
- return 22;
- case Tile::R23:
- case Tile::R23_32:
- return 23;
- case Tile::R24:
- case Tile::R24_32:
- return 24;
- case Tile::R25:
- case Tile::R25_32:
- return 25;
- case Tile::R26:
- case Tile::R26_32:
- return 26;
- case Tile::R27:
- case Tile::R27_32:
- return 27;
- case Tile::R28:
- case Tile::R28_32:
- return 28;
- case Tile::R29:
- case Tile::R29_32:
- return 29;
- case Tile::R30:
- case Tile::R30_32:
- return 30;
- case Tile::R31:
- case Tile::R31_32:
- return 31;
- case Tile::R32:
- case Tile::R32_32:
- return 32;
- case Tile::R33:
- case Tile::R33_32:
- return 33;
- case Tile::R34:
- case Tile::R34_32:
- return 34;
- case Tile::R35:
- case Tile::R35_32:
- return 35;
- case Tile::R36:
- case Tile::R36_32:
- return 36;
- case Tile::R37:
- case Tile::R37_32:
- return 37;
- case Tile::R38:
- case Tile::R38_32:
- return 38;
- case Tile::R39:
- case Tile::R39_32:
- return 39;
- case Tile::R40:
- case Tile::R40_32:
- return 40;
- case Tile::R41:
- case Tile::R41_32:
- return 41;
- case Tile::R42:
- case Tile::R42_32:
- return 42;
- case Tile::R43:
- case Tile::R43_32:
- return 43;
- case Tile::R44:
- case Tile::R44_32:
- return 44;
- case Tile::R45:
- case Tile::R45_32:
- return 45;
- case Tile::R46:
- case Tile::R46_32:
- return 46;
- case Tile::R47:
- case Tile::R47_32:
- return 47;
- case Tile::R48:
- case Tile::R48_32:
- return 48;
- case Tile::R49:
- case Tile::R49_32:
- return 49;
- case Tile::R50:
- case Tile::R50_32:
- return 50;
- case Tile::R51:
- case Tile::R51_32:
- return 51;
- case Tile::FP:
- case Tile::FP_32:
- return 52;
- case Tile::TP:
- case Tile::TP_32:
- return 53;
- case Tile::SP:
- case Tile::SP_32:
- return 54;
- case Tile::LR:
- case Tile::LR_32:
- return 55;
- case Tile::ZERO:
- case Tile::ZERO_32:
- return 63;
- default:
- llvm_unreachable("Unknown register number!");
- }
-}
-
inline static std::pair<const MCSymbolRefExpr *, int64_t>
TileGetSymAndOffset(const MCFixup &Fixup) {
MCFixupKind FixupKind = Fixup.getKind();
diff --git a/lib/Target/Tile/MCTargetDesc/TileMCCodeEmitter.cpp b/lib/Target/Tile/MCTargetDesc/TileMCCodeEmitter.cpp
index d4c658d..0fc1554 100644
--- a/lib/Target/Tile/MCTargetDesc/TileMCCodeEmitter.cpp
+++ b/lib/Target/Tile/MCTargetDesc/TileMCCodeEmitter.cpp
@@ -19,6 +19,7 @@
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
@@ -204,7 +205,7 @@ unsigned TileMCCodeEmitter::getMachineOpValue(
(IssueSlot == TileII::ST_Solo) ? 1 : IssueSlot - 1;
if (MO.isReg()) {
- return getTileRegisterNumbering(MO.getReg());
+ return Ctx.getRegisterInfo().getEncodingValue(MO.getReg());
} else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm());
} else if (MO.isFPImm()) {
diff --git a/lib/Target/Tile/TileRegisterInfo.td b/lib/Target/Tile/TileRegisterInfo.td
index 60356de..3e302c1 100644
--- a/lib/Target/Tile/TileRegisterInfo.td
+++ b/lib/Target/Tile/TileRegisterInfo.td
@@ -15,26 +15,23 @@ let Namespace = "Tile" in {
}
// We have banks of 32 registers each.
-class TileReg<string n> : Register<n> {
- field bits<6> Num;
+class TileReg<bits<16> Enc, string n> : Register<n> {
+ let HWEncoding = Enc;
let Namespace = "Tile";
}
-class TileRegWithSubRegs<string n, list<Register> subregs>
+class TileRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
: RegisterWithSubRegs<n, subregs> {
- field bits<6> Num;
+ let HWEncoding = Enc;
let Namespace = "Tile";
}
// Tile CPU Registers.
-class TileGPRReg<bits<6> num, string n> : TileReg<n> {
- let Num = num;
-}
+class TileGPRReg<bits<16> Enc, string n> : TileReg<Enc, n>;
// Tile 64-bit CPU Registers.
-class Tile64GPRReg<bits<6> num, string n, list<Register> subregs>
- : TileRegWithSubRegs<n, subregs> {
- let Num = num;
+class Tile64GPRReg<bits<16> Enc, string n, list<Register> subregs>
+ : TileRegWithSubRegs<Enc, n, subregs> {
let SubRegIndices = [sub_32];
}
-------------- next part --------------
diff --git a/lib/Target/Tile/TileISelLowering.cpp b/lib/Target/Tile/TileISelLowering.cpp
index c59e0b7..a11fcc0 100644
--- a/lib/Target/Tile/TileISelLowering.cpp
+++ b/lib/Target/Tile/TileISelLowering.cpp
@@ -814,7 +814,7 @@ static bool CC_TileByval(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
CCState &State) {
unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned) 8);
- unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8;
+ unsigned Size = RoundUpToAlignment(ArgFlags.getByValSize(), Align);
unsigned FirstIdx = State.getFirstUnallocated(TileIntRegs, TILEGX_AREG_NUM);
assert(Align <= 16 && "Cannot handle alignments larger than 16.");
@@ -868,16 +868,16 @@ static void AnalyzeTileCallOperands(
// Copy Tile byVal arg to registers and stack.
void TileTargetLowering::passByValArg(
- SDValue &ByValChain, SDValue Chain, DebugLoc dl,
+ SDValue Chain, DebugLoc dl,
SmallVector<std::pair<unsigned, SDValue>, TILEGX_AREG_NUM> &RegsToPass,
- SmallVector<SDValue, 8> &MemOpChains, int &LastFI, MachineFrameInfo *MFI,
- SelectionDAG &DAG, SDValue Arg, const CCValAssign &VA,
- const ISD::ArgFlagsTy &Flags) const {
+ SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
+ MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
+ const CCValAssign &VA, const ISD::ArgFlagsTy &Flags) const {
unsigned ByValSize = Flags.getByValSize();
- unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned) 8);
+ unsigned Align = std::max(Flags.getByValAlign(), (unsigned) 8);
bool IsRegLoc = VA.isRegLoc();
unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
- unsigned LocMemOffset = 0;
+ unsigned LocMemOffset = TILEGX_BZONE_SIZE;
unsigned MemCpySize = ByValSize;
EVT PtrTy = getPointerTy();
@@ -892,7 +892,7 @@ void TileTargetLowering::passByValArg(
DAG.getNode(ISD::ADD, dl, PtrTy, Arg, DAG.getConstant(Offset, PtrTy));
SDValue LoadVal =
DAG.getLoad(MVT::i64, dl, Chain, LoadPtr, MachinePointerInfo(), false,
- false, false, Alignment);
+ false, false, Align);
MemOpChains.push_back(LoadVal.getValue(1));
RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
}
@@ -917,7 +917,7 @@ void TileTargetLowering::passByValArg(
DAG.getConstant(Offset, PtrTy));
SDValue LoadVal = DAG.getExtLoad(
ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr, MachinePointerInfo(),
- MVT::getIntegerVT(LoadSize * 8), false, false, Alignment);
+ MVT::getIntegerVT(LoadSize * 8), false, false, Align);
MemOpChains.push_back(LoadVal.getValue(1));
// Offset in number of bits from double word boundary.
@@ -929,7 +929,7 @@ void TileTargetLowering::passByValArg(
Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift)
: Shift;
Offset += LoadSize;
- Alignment = std::min(Alignment, LoadSize);
+ Align = std::min(Align, LoadSize);
}
RegsToPass.push_back(std::make_pair(*Reg, Val));
@@ -940,16 +940,17 @@ void TileTargetLowering::passByValArg(
assert(MemCpySize && "MemCpySize must not be zero.");
- // Create a fixed object on stack at offset LocMemOffset and copy
- // remainder of byval arg to it with memcpy.
+ // Copy remainder of byval arg to it with memcpy.
SDValue Src =
DAG.getNode(ISD::ADD, dl, PtrTy, Arg, DAG.getConstant(Offset, PtrTy));
- LastFI = MFI->CreateFixedObject(MemCpySize, LocMemOffset, true);
- SDValue Dst = DAG.getFrameIndex(LastFI, PtrTy);
- ByValChain = DAG.getMemcpy(
- ByValChain, dl, Dst, Src, DAG.getConstant(MemCpySize, PtrTy), Alignment,
- /*isVolatile=*/ false, /*AlwaysInline=*/ false, MachinePointerInfo(0),
- MachinePointerInfo(0));
+ SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrTy, StackPtr,
+ DAG.getConstant(LocMemOffset, PtrTy));
+
+ Chain = DAG.getMemcpy(Chain, dl, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
+ Align, /*isVolatile=*/ false, /*AlwaysInline=*/ false,
+ MachinePointerInfo(0), MachinePointerInfo(0));
+
+ MemOpChains.push_back(Chain);
}
// Functions arguments are copied from virtual regs to
@@ -991,7 +992,6 @@ SDValue TileTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SDValue Chain, CallSeqStart, ByValChain;
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal);
- ByValChain = InChain;
unsigned MaxCallFrameSize = TileFI->getMaxCallFrameSize();
@@ -1003,7 +1003,6 @@ SDValue TileTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVector<std::pair<unsigned, SDValue>, TILEGX_AREG_NUM> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
- int LastFI = 0;
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
SDValue Arg = OutVals[i];
@@ -1015,8 +1014,8 @@ SDValue TileTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (Flags.isByVal()) {
assert(Flags.getByValSize() &&
"ByVal args of size 0 should have been ignored by front-end.");
- passByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, MFI,
- DAG, Arg, VA, Flags);
+ passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
+ VA, Flags);
continue;
}
@@ -1061,12 +1060,6 @@ SDValue TileTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
MachinePointerInfo(), false, false, 0));
}
- // If a memcpy has been created to copy a byval arg to a stack, replace the
- // chain input of CallSeqStart with ByValChain.
- if (InChain != ByValChain)
- DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain,
- NextStackOffsetVal);
-
// Transform all store nodes into one single node because all store
// nodes are independent of each other.
if (!MemOpChains.empty())
@@ -1180,22 +1173,39 @@ static unsigned CopyTileByValRegs(
SmallVectorImpl<SDValue> &InVals, TileFunctionInfo *TileFI, EVT PtrTy,
const Argument *FuncArg) {
const uint16_t *Reg = TileIntRegs + TILEGX_AREG_NUM;
- int FOOffset; // Frame object offset from virtual frame pointer.
+ int FOOffset;
+ int ByRegSize = 0;
+ int ByMemSize = 0;
+ unsigned Align = std::max(Flags.getByValAlign(), (unsigned) 8);
+ int ByValSize = RoundUpToAlignment(Flags.getByValSize(), Align);
if (IsRegLoc) {
Reg = std::find(TileIntRegs, TileIntRegs + TILEGX_AREG_NUM, VA.getLocReg());
- FOOffset = (Reg - TileIntRegs) * 8 - TILEGX_AREG_NUM * 8;
+ // For Tilegx, the stack layout looks like:
+ //
+ // -----
+ //
+ // Out going
+ // -----
+ //
+ // 16bytes reserved
+ // -----
+ //
+ //
+ // ----- <- FOOffset
+ FOOffset = -ByValSize;
+ ByRegSize = (TILEGX_AREG_NUM - (Reg - TileIntRegs)) * 8;
+ ByMemSize = ByValSize - ByRegSize;
} else
FOOffset = VA.getLocMemOffset();
// Create frame object.
- unsigned NumRegs = (Flags.getByValSize() + 7) / 8;
- unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true);
+ unsigned LastFI = MFI->CreateFixedObject(ByValSize, FOOffset, true);
SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy);
InVals.push_back(FIN);
// Copy arg registers.
- for (unsigned I = 0;(Reg != TileIntRegs + TILEGX_AREG_NUM) && (I < NumRegs);
+ for (int I = 0;(Reg != TileIntRegs + TILEGX_AREG_NUM) && (I * 8) < ByValSize;
++Reg, ++I) {
unsigned VReg = AddLiveIn(MF, *Reg, &Tile::CPURegsRegClass);
SDValue StorePtr =
@@ -1206,6 +1216,22 @@ static unsigned CopyTileByValRegs(
OutChains.push_back(Store);
}
+ if (ByMemSize) {
+ SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
+ DAG.getConstant(ByRegSize, PtrTy));
+
+ SDValue Src =
+ DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
+ DAG.getConstant(ByValSize + TILEGX_BZONE_SIZE, PtrTy));
+
+ Chain =
+ DAG.getMemcpy(Chain, dl, Dst, Src, DAG.getConstant(ByMemSize, PtrTy), 8,
+ /*isVolatile=*/ false, /*AlwaysInline=*/ false,
+ MachinePointerInfo(0), MachinePointerInfo(0));
+
+ OutChains.push_back(Chain);
+ }
+
return LastFI;
}
@@ -1233,7 +1259,7 @@ SDValue TileTargetLowering::LowerFormalArguments(
Function::const_arg_iterator FuncArg =
DAG.getMachineFunction().getFunction()->arg_begin();
- int LastFI = 0; // TileFI->LastInArgFI is 0 at the entry of this function.
+ int LastFI = 0;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) {
CCValAssign &VA = ArgLocs[i];
diff --git a/lib/Target/Tile/TileISelLowering.h b/lib/Target/Tile/TileISelLowering.h
index a22c430..310349f 100644
--- a/lib/Target/Tile/TileISelLowering.h
+++ b/lib/Target/Tile/TileISelLowering.h
@@ -137,11 +137,11 @@ private:
// Copy Tile byVal arg to registers and stack.
void passByValArg(
- SDValue &ByValChain, SDValue Chain, DebugLoc dl,
+ SDValue Chain, DebugLoc dl,
SmallVector<std::pair<unsigned, SDValue>, TILEGX_AREG_NUM> &RegsToPass,
- SmallVector<SDValue, 8> &MemOpChains, int &LastFI, MachineFrameInfo *MFI,
- SelectionDAG &DAG, SDValue Arg, const CCValAssign &VA,
- const ISD::ArgFlagsTy &Flags) const;
+ SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
+ MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
+ const CCValAssign &VA, const ISD::ArgFlagsTy &Flags) const;
// Inline asm support.
ConstraintType getConstraintType(const std::string &Constraint) const;
More information about the llvm-commits
mailing list