[llvm] r178142 - Print PPC ZERO as 0 (not r0) even on Darwin

Hal Finkel hfinkel at anl.gov
Wed Mar 27 06:20:53 PDT 2013


Author: hfinkel
Date: Wed Mar 27 08:20:52 2013
New Revision: 178142

URL: http://llvm.org/viewvc/llvm-project?rev=178142&view=rev
Log:
Print PPC ZERO as 0 (not r0) even on Darwin

It seems that the Darwin PPC assembler requires r0 to be written as 0 when it
means 0 (at least in lwarx/stwcx.). Fixes PR15605.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
    llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=178142&r1=178141&r2=178142&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Wed Mar 27 08:20:52 2013
@@ -87,8 +87,8 @@ foreach Index = 0-31 in {
 }
 
 // The reprsentation of r0 when treated as the constant 0.
-def ZERO  : GPR<0, "r0">;
-def ZERO8 : GP8<ZERO, "r0">;
+def ZERO  : GPR<0, "0">;
+def ZERO8 : GP8<ZERO, "0">;
 
 // Representations of the frame pointer used by ISD::FRAMEADDR.
 def FP   : GPR<0 /* arbitrary */, "**FRAME POINTER**">;

Modified: llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll?rev=178142&r1=178141&r2=178142&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll Wed Mar 27 08:20:52 2013
@@ -1,10 +1,10 @@
-; RUN: llc < %s -march=ppc32 |  FileCheck %s
+; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 |  FileCheck %s
 
 define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
 ; CHECK: exchange_and_add:
-; CHECK: lwarx
+; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}}
   %tmp = atomicrmw add i32* %mem, i32 %val monotonic
-; CHECK: stwcx.
+; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}}
   ret i32 %tmp
 }
 





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