[llvm] r178114 - Remove the link register from the GPR classes on PowerPC.
Bill Schmidt
wschmidt at linux.vnet.ibm.com
Tue Mar 26 19:40:15 PDT 2013
Author: wschmidt
Date: Tue Mar 26 21:40:14 2013
New Revision: 178114
URL: http://llvm.org/viewvc/llvm-project?rev=178114&view=rev
Log:
Remove the link register from the GPR classes on PowerPC.
Some implementation detail in the forgotten past required the link
register to be placed in the GPRC and G8RC register classes. This is
just wrong on the face of it, and causes several extra intersection
register classes to be generated. I found this was having evil
effects on instruction scheduling, by causing the wrong register class
to be consulted for register pressure decisions.
No code generation changes are expected, other than some minor changes
in instruction order. Seven tests in the test bucket required minor
tweaks to adjust to the new normal.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll
llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll
llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll
llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll
llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll
llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll
llvm/trunk/test/CodeGen/PowerPC/tls.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=178114&r1=178113&r2=178114&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Tue Mar 26 21:40:14 2013
@@ -172,11 +172,11 @@ def RM: SPR<512, "**ROUNDING MODE**">;
// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
(sequence "R%u", 30, 13),
- R31, R0, R1, LR, FP)>;
+ R31, R0, R1, FP)>;
def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
(sequence "X%u", 30, 14),
- X31, X13, X0, X1, LR8, FP8)>;
+ X31, X13, X0, X1, FP8)>;
// For some instructions r0 is special (representing the value 0 instead of
// the value in the r0 register), and we use these register subclasses to
Modified: llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll?rev=178114&r1=178113&r2=178114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll Tue Mar 26 21:40:14 2013
@@ -23,22 +23,22 @@ entry:
; CHECK: std 4, 200(1)
; CHECK: std 3, 192(1)
; CHECK: lbz {{[0-9]+}}, 199(1)
-; CHECK: stb {{[0-9]+}}, 55(1)
; CHECK: lhz {{[0-9]+}}, 197(1)
+; CHECK: stb {{[0-9]+}}, 55(1)
; CHECK: sth {{[0-9]+}}, 53(1)
; CHECK: lbz {{[0-9]+}}, 207(1)
-; CHECK: stb {{[0-9]+}}, 63(1)
; CHECK: lwz {{[0-9]+}}, 203(1)
+; CHECK: stb {{[0-9]+}}, 63(1)
; CHECK: stw {{[0-9]+}}, 59(1)
; CHECK: lhz {{[0-9]+}}, 214(1)
-; CHECK: sth {{[0-9]+}}, 70(1)
; CHECK: lwz {{[0-9]+}}, 210(1)
+; CHECK: sth {{[0-9]+}}, 70(1)
; CHECK: stw {{[0-9]+}}, 66(1)
; CHECK: lbz {{[0-9]+}}, 223(1)
-; CHECK: stb {{[0-9]+}}, 79(1)
; CHECK: lhz {{[0-9]+}}, 221(1)
-; CHECK: sth {{[0-9]+}}, 77(1)
; CHECK: lwz {{[0-9]+}}, 217(1)
+; CHECK: stb {{[0-9]+}}, 79(1)
+; CHECK: sth {{[0-9]+}}, 77(1)
; CHECK: stw {{[0-9]+}}, 73(1)
; CHECK: ld 6, 72(1)
; CHECK: ld 5, 64(1)
Modified: llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll?rev=178114&r1=178113&r2=178114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll Tue Mar 26 21:40:14 2013
@@ -114,8 +114,8 @@ entry:
ret i32 %add13
; CHECK: lha {{[0-9]+}}, 126(1)
-; CHECK: lbz {{[0-9]+}}, 119(1)
; CHECK: lha {{[0-9]+}}, 132(1)
+; CHECK: lbz {{[0-9]+}}, 119(1)
; CHECK: lwz {{[0-9]+}}, 140(1)
; CHECK: lwz {{[0-9]+}}, 144(1)
; CHECK: lwz {{[0-9]+}}, 152(1)
@@ -206,8 +206,8 @@ entry:
ret i32 %add13
; CHECK: lha {{[0-9]+}}, 126(1)
-; CHECK: lbz {{[0-9]+}}, 119(1)
; CHECK: lha {{[0-9]+}}, 133(1)
+; CHECK: lbz {{[0-9]+}}, 119(1)
; CHECK: lwz {{[0-9]+}}, 140(1)
; CHECK: lwz {{[0-9]+}}, 147(1)
; CHECK: lwz {{[0-9]+}}, 154(1)
Modified: llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll?rev=178114&r1=178113&r2=178114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll Tue Mar 26 21:40:14 2013
@@ -105,8 +105,8 @@ entry:
; CHECK: sth 4, 62(1)
; CHECK: stb 3, 55(1)
; CHECK: lha {{[0-9]+}}, 62(1)
-; CHECK: lbz {{[0-9]+}}, 55(1)
; CHECK: lha {{[0-9]+}}, 68(1)
+; CHECK: lbz {{[0-9]+}}, 55(1)
; CHECK: lwz {{[0-9]+}}, 76(1)
; CHECK: lwz {{[0-9]+}}, 80(1)
; CHECK: lwz {{[0-9]+}}, 88(1)
@@ -192,8 +192,8 @@ entry:
; CHECK: sth 4, 62(1)
; CHECK: stb 3, 55(1)
; CHECK: lha {{[0-9]+}}, 62(1)
-; CHECK: lbz {{[0-9]+}}, 55(1)
; CHECK: lha {{[0-9]+}}, 69(1)
+; CHECK: lbz {{[0-9]+}}, 55(1)
; CHECK: lwz {{[0-9]+}}, 76(1)
; CHECK: lwz {{[0-9]+}}, 83(1)
; CHECK: lwz {{[0-9]+}}, 90(1)
Modified: llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll?rev=178114&r1=178113&r2=178114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll Tue Mar 26 21:40:14 2013
@@ -18,6 +18,6 @@ entry:
; CHECK: addis [[REG:[0-9]+]], 2, a at got@tlsgd at ha
; CHECK-NEXT: addi 3, [[REG]], a at got@tlsgd at l
-; CHECK-NEXT: bl __tls_get_addr(a at tlsgd)
+; CHECK: bl __tls_get_addr(a at tlsgd)
; CHECK-NEXT: nop
Modified: llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll?rev=178114&r1=178113&r2=178114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll Tue Mar 26 21:40:14 2013
@@ -18,7 +18,7 @@ entry:
; CHECK: addis [[REG:[0-9]+]], 2, a at got@tlsld at ha
; CHECK-NEXT: addi 3, [[REG]], a at got@tlsld at l
-; CHECK-NEXT: bl __tls_get_addr(a at tlsld)
+; CHECK: bl __tls_get_addr(a at tlsld)
; CHECK-NEXT: nop
-; CHECK-NEXT: addis [[REG2:[0-9]+]], 3, a at dtprel@ha
+; CHECK: addis [[REG2:[0-9]+]], 3, a at dtprel@ha
; CHECK-NEXT: lwa {{[0-9]+}}, a at dtprel@l([[REG2]])
Modified: llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll?rev=178114&r1=178113&r2=178114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll Tue Mar 26 21:40:14 2013
@@ -18,7 +18,7 @@ entry:
; CHECK: addis [[REG:[0-9]+]], 2, a at got@tlsld at ha
; CHECK-NEXT: addi 3, [[REG]], a at got@tlsld at l
-; CHECK-NEXT: bl __tls_get_addr(a at tlsld)
+; CHECK: bl __tls_get_addr(a at tlsld)
; CHECK-NEXT: nop
-; CHECK-NEXT: addis [[REG2:[0-9]+]], 3, a at dtprel@ha
+; CHECK: addis [[REG2:[0-9]+]], 3, a at dtprel@ha
; CHECK-NEXT: addi {{[0-9]+}}, [[REG2]], a at dtprel@l
Modified: llvm/trunk/test/CodeGen/PowerPC/tls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls.ll?rev=178114&r1=178113&r2=178114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls.ll Tue Mar 26 21:40:14 2013
@@ -12,7 +12,7 @@ entry:
;OPT0: addis [[REG1:[0-9]+]], 13, a at tprel@ha
;OPT0-NEXT: li [[REG2:[0-9]+]], 42
;OPT0-NEXT: addi [[REG1]], [[REG1]], a at tprel@l
-;OPT0-NEXT: stw [[REG2]], 0([[REG1]])
+;OPT0: stw [[REG2]], 0([[REG1]])
;OPT1: addis [[REG1:[0-9]+]], 13, a at tprel@ha
;OPT1-NEXT: li [[REG2:[0-9]+]], 42
;OPT1-NEXT: stw [[REG2]], a at tprel@l([[REG1]])
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