[llvm] r178023 - R600/SI: improve vector interpolation

[Christian Konig]

Author: ckoenig
Date: Tue Mar 26 09:04:12 2013
New Revision: 178023

URL: http://llvm.org/viewvc/llvm-project?rev=178023&view=rev
Log:
R600/SI: improve vector interpolation

Prevent loading M0 multiple times.

Signed-off-by: Christian König <christian.koenig at amd.com>

Modified:
    llvm/trunk/lib/Target/R600/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=178023&r1=178022&r2=178023&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.cpp Tue Mar 26 09:04:12 2013
@@ -65,6 +65,26 @@ SIInstrInfo::copyPhysReg(MachineBasicBlo
   unsigned Opcode;
   const int16_t *SubIndices;
 
+  if (AMDGPU::M0 == DestReg) {
+    // Check if M0 isn't already set to this value
+    for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
+      I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
+
+      if (!I->definesRegister(AMDGPU::M0))
+        continue;
+
+      unsigned Opc = I->getOpcode();
+      if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
+        break;
+
+      if (!I->readsRegister(SrcReg))
+        break;
+
+      // The copy isn't necessary
+      return;
+    }
+  }
+
   if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
     assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
     BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)