[llvm] r177404 - Cleanup PPC64 unaligned i64 load/store

Hal Finkel hfinkel at anl.gov
Tue Mar 19 08:23:39 PDT 2013


Author: hfinkel
Date: Tue Mar 19 10:23:39 2013
New Revision: 177404

URL: http://llvm.org/viewvc/llvm-project?rev=177404&view=rev
Log:
Cleanup PPC64 unaligned i64 load/store

Remove an accidentally-added instruction definition and add a comment in the
test case. This is in response to a post-commit review by Bill Schmidt.

No functionality change intended.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
    llvm/trunk/test/CodeGen/PowerPC/unal4-std.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=177404&r1=177403&r2=177404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Tue Mar 19 10:23:39 2013
@@ -683,10 +683,6 @@ def LDtoc_restore : DSForm_1a<58, 0, (ou
 def LDX  : XForm_1<31,  21, (outs G8RC:$rD), (ins memrr:$src),
                    "ldx $rD, $src", LdStLD,
                    [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
-let isCodeGenOnly = 1 in
-def LDXu  : XForm_1<31,  21, (outs G8RC:$rD), (ins memrr:$src),
-                    "ldx $rD, $src", LdStLD,
-                    [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
                    
 let mayLoad = 1 in
 def LDU  : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),

Modified: llvm/trunk/test/CodeGen/PowerPC/unal4-std.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/unal4-std.ll?rev=177404&r1=177403&r2=177404&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/unal4-std.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/unal4-std.ll Tue Mar 19 10:23:39 2013
@@ -17,6 +17,9 @@ vector.body.i:
 if.end210:                                        ; preds = %entry
   ret void
 
+; This will generate two align-1 i64 stores. Make sure that they are
+; indexed stores and not in r+i form (which require the offset to be
+; a multiple of 4).
 ; CHECK: @copy_to_conceal
 ; CHECK: stdx {{[0-9]+}}, 0,
 }





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