Fix for PR14824: Optimization arm_ldst_opt inserts newly generated instruction vldmia at incorrect position

[hao liu]

Hi Stepan,

I verified your patch. It worked well.

But I just have one question: do we need to consider about the mix
situation of registers of S, D and Q?  I just wonder the existence of some
code like:
      S1 = ldr r0, #4;
      D1 = ldr r0, #8;
      Q1 = ldr r0, #16;
      ...

Sorry that I don't know too much about backend. If we need to consider
about that situation, your patch looks very good.

Thanks,
- Hao

2013/3/12 Stepan Dyatkovskiy <stpworld at narod.ru>

> Hello!
> Please consider patch in attachment as fix for PR14824: Optimization
> arm_ldst_opt inserts newly generated instruction vldmia at incorrect
> position.
> Patch introduces memory operands tracking in ARMLoadStoreOpt::**LoadStoreMultipleOpti.
> For each register it keeps the order of load operations as it was before
> optimization pass.
> It is kind of deep improvement of fix proposed by Hao:
> http://llvm.org/bugs/show_bug.**cgi?id=14824#c4<http://llvm.org/bugs/show_bug.cgi?id=14824#c4>
> But it also tracks conflicts between different register classes (e.g. D2
> and S5).
>
> -Stepan
>
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